Frequency adapter utilized in high-speed internal buses
View Patent ↗A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization unit is clocked by a low frequency clock.
1. A frequency adapter for synchronizing data transfers between a low-frequency module configured to operate at a first frequency and a high-frequency module configured to operate at a second frequency, the second frequency being higher than the first frequency, comprising:
a low-to-high frequency synchronization unit configured to receive a plurality of data bursts from the low-frequency module, each of the plurality of data bursts including a plurality of data packets, to store the plurality of data packets in a buffer, and to provide a signal indicative of whether the buffer is empty;
an end of burst (EOB) unit configured to track a number of the plurality of data bursts stored in the buffer and to provide an EOB-enabled signal when the number is greater than zero;
a first logic device configured to provide a valid fast signal based on the signal and the EOB-enabled signal; and
a second logic device configured to provide a POP signal based on the valid fast signal and an acknowledgement (ACK) signal, the ACK signal being indicative that the high-frequency module is ready to receive data,
wherein the low-to-high frequency synchronization unit is further configured to transfer the plurality of data packets from the buffer to the high-frequency module based on the POP signal.
2. The frequency adapter of claim 1 , wherein the buffer comprises:
a first-in-first-out (FIFO) buffer.
3. The frequency adapter of claim 1 , wherein the low-to-high frequency synchronization unit is further configured to transfer the plurality of data packets to the high-frequency module in continuous data bursts.
4. The frequency adapter of claim 1 , wherein the EOB unit is further configured to provide the EOB-enabled signal based on an EOB slow signal, the EOB slow signal being indicative of a valid data burst transaction at the low-frequency module.
5. The frequency adapter of claim 1 , further comprising:
a high-to-low-frequency synchronization unit configured to transfer another plurality of data packets from the high-frequency module to the low-frequency module in response to a second ACK signal, the second ACK signal being indicative that the low-frequency module is ready to receive data.
6. The frequency adapter of claim 5 , wherein the high-to-low-frequency synchronization unit and the low-to-high frequency synchronization unit are respectively connected to a first basic bus unit and a second basic bus unit of an internal bus.
7. The frequency adapter of claim 1 , wherein the low-to-high frequency synchronization unit is further configured to transfer the plurality of data packets from the buffer to the high-frequency module at a rate of the second frequency.
8. The frequency adapter of claim 1 , wherein the second frequency is proportional to the first frequency.
9. In an integrated circuit, a method for synchronizing data between a first module and a second module operating at different frequencies, comprising:
receiving a plurality of data bursts from the first module, each of the plurality of data bursts including a plurality of data packets;
storing the plurality of data packets in a buffer;
generating a signal indicative of whether the buffer is empty;
tracking a number of the plurality of data bursts stored in the buffer;
generating an end-of-burst (EOB)-enabled signal when the number is greater than zero;
generating a valid fast signal based on a first logical AND operation of the signal and the EOB-enabled signal;
generating a POP signal based on a second logical AND operation of the valid fast signal and an acknowledgement (ACK) signal, the ACK signal being indicative that the second module is ready to receive data; and
transferring the plurality of data packets from the buffer to the second module based on the POP signal, the signal, and the EOB-enabled signal.
10. The method of claim 9 , wherein the transferring comprises:
transferring the plurality of data packets to the second nodule in continuous data bursts.
11. The method of claim 9 , further comprising:
transferring another plurality of data packets from the second module to the first module based on a second ACK signal, the second ACK signal being indicative that the first module is ready to receive data.
12. The method of claim 9 , wherein the first module is configured to operate at a first frequency, wherein the second module is configured to operate at a second frequency, and wherein the transferring comprises:
transferring the plurality of data packets from the buffer to the second module at a rate of the second frequency.
13. The method of claim 9 , wherein the generating the EOB-signal comprises:
generating the EOB-enabled signal based on an EOB slow signal,
wherein the EOB slow signal is indicative of a valid data burst at the first module.
14. A frequency adapter for synchronizing data transfers between a first module and a second module operating at different frequencies, comprising:
a first frequency synchronization unit configured to receive a data burst from the first frequency module, the data burst including a plurality of data packets, and to store the plurality of data packets in a buffer;
a second frequency synchronization unit configured to transfer another plurality of data packets from the second module to the first module based on an acknowledgement (ACK) signal, the ACK signal being indicative that the first module is ready to receive the another plurality of data packets; and
an end of burst (EOB) unit configured to track a number of the plurality of data bursts stored in the buffer and to assert an EOB-enabled signal when the number is greater than zero,
wherein the first frequency synchronization unit is further configured to assert a signal when the buffer is not empty and to transfer the plurality of data packets to the second module when the signal and the EOB-enabled signal are asserted and the second module is ready to receive the plurality of data packets.
15. The frequency adapter of claim 14 , wherein the first module is configured to operate at a first frequency, wherein the second module is configured to operate at a second frequency, and wherein the first frequency is proportional to the second frequency.
16. The frequency adapter of claim 15 , wherein the first frequency synchronization unit comprises:
a sampler configured to sample the plurality of data packets at a rate of the first frequency, and
wherein the buffer is further configured to store the plurality of data packets at the rate of the first frequency.
17. The frequency adapter of claim 16 , wherein the first frequency synchronization unit is further configured to transfer the plurality of data packets from the buffer to the second module at a rate of the second frequency.
18. The frequency adapter of claim 16 , wherein the first frequency synchronization unit is further configured to transfer the plurality of data packets to the second module in continuous data bursts.