Apparatus and method for buffering data between memory controller and DRAM
View Patent ↗A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.
1. An apparatus for buffering a data signal between a memory controller and a DRAM, the apparatus comprising:
a phase locked loop (PLL);
a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word; and
a non-volatile storage location that stores the phase aligning control word, wherein the phase aligning control word is determined through an initial training procedure of the apparatus using predetermined training conditions,
wherein the predetermined training condition include at least a predetermined supply voltage level and a predetermined temperature, and
wherein the predetermined training conditions are set so as to generally optimize the phase alignment of an edge of the output clock signal with respect to a buffered data signal,
wherein the predetermined training conditions during the initial training are set apart from the middle of at least two corners of the training conditions so as to comply with an asymmetric behavior of the phase with respect to the training conditions,
wherein the buffered signal is derived from information derived from these training conditions,
wherein the corners are a maximum supply voltage with a minimum temperature and a minimum supply voltage with maximum temperature.
2. The apparatus according to claim 1 , wherein a plurality of non-volatile storage locations is provided for storing a plurality of phase aligning control words for different operating clock frequencies and/or supply voltage levels.
3. A method of buffering data between a memory controller and a DRAM and aligning a phase of an output clock signal with respect to the data, the method comprising:
setting predetermined training conditions of at least a supply voltage and a temperature;
performing a training procedure;
determining a phase aligning control word indicating the optimized phase alignment of the output clock signal under the predetermined training conditions;
storing the phase aligning control word in a non volatile memory in the apparatus; and
running the apparatus with the stored phase aligning control word under normal operating conditions,
wherein the method further comprises setting the predetermined training conditions apart from the middle of corners,
wherein the buffered signal is derived from information derived from these training conditions,
wherein the corners are a maximum supply voltage with a minimum temperature and a minimum supply voltage with a maximum temperature.
4. The method according to claim 3 , wherein the method further comprises storing a plurality of phase aligning control words for different operating clock frequencies and/or supply voltage levels of the apparatus.