IP Library Granted Patent US 8,288,232
Granted Patent B2
US 8,288,232 · App. 12/687,110 · Granted Oct 16, 2012

Manufacturing method of semiconductor device and semiconductor device

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Quick Facts
Patent No.
US 8,288,232
App. No.
12/687,110
Granted
Oct 16, 2012
Kind
B2
Abstract

An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor.

Claims (24)

1. A manufacturing method of a semiconductor device, comprising the step of:

forming, in a semiconductor substrate, a first transistor and a second transistor which have respective gate insulating films of different thicknesses,

wherein the step of forming the first transistor and the second transistor includes the steps of

(a) forming a first insulating film over the semiconductor substrate;

(b) abrading a surface of the first insulating film to reduce a thickness thereof;

(c) forming, over the semiconductor substrate and in adjacent relation to the first insulating film, a second insulating film in a region other than a region where the first insulating film is formed;

(d) after the step (c), successively forming a first silicon film and a protective silicone nitride film so as to cover the first insulating film and the second insulating film therewith;

(e) after the step (d), forming, in a two-dimensional boundary portion between the first insulating film and the second insulating film, a trench portion for isolation extending in a direction of a depth of the semiconductor substrate;

(f) after the step (e), forming an insulating film for isolation so as to fill the trench portion for isolation therewith;

(g) after step (f), removing the insulating film for isolation deposited over a portion other than in the trench portion for isolation; and

(h) after the step (g), removing the protective silicon nitride film,

wherein, in the step (a), the first insulating film is formed by a thermal oxidation method so as to extend from an inside of a main surface of the semiconductor substrate to an outside thereof,

wherein, in the step (c), the second insulating film is formed so as to be thinner than the first insulating film,

wherein the first insulating film is formed as the gate insulating film of the first transistor, and the second insulating film is formed as the gate insulating film of the second transistor,

wherein, by the steps (e) to (g), an isolation portion is formed by filling the trench portion for isolation with the insulating film for isolation,

wherein the first transistor and the second transistor are formed to be spaced apart from each other by the isolation portion,

wherein, in the step (e), the trench portion for isolation is formed so as to extend through the first silicon film and the protective silicon nitride film,

wherein, in the step (g), CMP is performed with respect to the insulating film for isolation using the protective silicon nitride film as a CMP stop film to remove the insulating film for isolation, and

wherein, in the step (h), etching is performed with respect to the protective silicon nitride film using the first silicon film as an etching stop film to remove the protective silicon nitride film.

2. The manufacturing method of a semiconductor device according to claim 1 , further comprising the steps of:

(i) after the step (h), forming a second silicon film over the first silicon film and the insulating film; and

(j) after the step (i), selectively etching the second silicon film such that the second silicon film is kept on the first silicon film.

3. The manufacturing method of a semiconductor device according to claim 2 ,

wherein the first and second silicon films are formed as gate electrodes of the first and second transistors.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2024
From: SYNAPTICS JAPAN GK
To: SYNAPTICS INCORPORATED
Reel/Frame 067793/0211 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
CHANGE OF NAME Recorded Aug 8, 2016
From: SYNAPTICS DISPLAY DEVICES GK
To: SYNAPTICS JAPAN GK
Reel/Frame 039711/0862 →
CHANGE OF NAME Recorded May 29, 2015
From: RENESAS SP DRIVERS INC.
To: SYNAPTICS DISPLAY DEVICES KK
Reel/Frame 035796/0947 →
CHANGE OF NAME Recorded May 29, 2015
From: SYNAPTICS DISPLAY DEVICES KK
To: SYNAPTICS DISPLAY DEVICES GK
Reel/Frame 035797/0036 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2014
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS SP DRIVERS INC.
Reel/Frame 033778/0137 →
CHANGE OF NAME Recorded Aug 13, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024864/0635 →
MERGER Recorded Aug 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0190 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: FUJII, YASUHIRO; YONEKURA, KAZUMASA; KANEOKA, TATSUNORI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 023784/0933 →