Balancing NFET and PFET performance using straining layers
View Patent ↗An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
1. An integrated circuit structure comprising:
a substrate;
at least one pair of complementary transistors one of on and in said substrate, said pair of complementary transistors comprising a first transistor and a second transistor;
a first stress-producing layer on said first transistor and said second transistor; and
a second stress-producing layer on said first stress-producing layer over said first transistor and said second transistor,
said first stress-producing layer applying tensile strain force on said first transistor and said second transistor, and
said second stress-producing layer applying compressive strain force on said first stress-producing layer, said first transistor, and said second transistor.
2. The integrated circuit structure according to claim 1 , said pair of complementary transistors comprising complementary metal oxide (CMOS) transistors.
3. The integrated circuit structure according to claim 1 , said first transistor comprising a negative-type (N-type) transistor and said second transistor comprising a positive-type (P-type) transistor.
4. The integrated circuit structure according to claim 3 , said second transistor comprising a silicon germanium channel and said first transistor comprising a silicon channel free of germanium.
5. The integrated circuit structure according to claim 1 , said first stress-producing layer and said second stress-producing layer comprising at least one of silicon-germanium, silicon-nitride, and silicon-carbon.
6. An integrated circuit structure comprising:
a substrate;
at least one pair of complementary transistors one of on and in said substrate, said pair of complementary transistors comprising a first transistor and a second transistor;
a first stress-producing layer on said first transistor and said second transistor; and
a second stress-producing layer on said first stress-producing layer over said first transistor and said second transistor,
said first stress-producing layer applying tensile strain force on said first transistor and said second transistor,
said second stress-producing layer applying compressive strain force on said first stress-producing layer, said first transistor, and said second transistor,
said first stress-producing layer and said second stress-producing layer comprising different thicknesses, and
a difference in thickness between said first stress-producing layer and said second stress-producing layer altering performance of said first transistor and said second transistor.
7. The integrated circuit structure according to claim 6 , said pair of complementary transistors comprising complementary metal oxide (CMOS) transistors.
8. The integrated circuit structure according to claim 6 , said first transistor comprising a negative-type (N-type) transistor and said second transistor comprising a positive-type (P-type) transistor.
9. The integrated circuit structure according to claim 8 , said second transistor comprising a silicon germanium channel and said first transistor comprising a silicon channel free of germanium.
10. The integrated circuit structure according to claim 6 , said first stress-producing layer and said second stress-producing layer comprising at least one of silicon-germanium, silicon-nitride, and silicon-carbon.
11. A method of manufacturing an integrated circuit structure, said method comprising:
forming at least one pair of complementary transistors one of on and in a wafer, said pair of complementary transistors comprising a first transistor and a second transistor; and
forming a first stress-producing layer on said first transistor and said second transistor, said first stress-producing layer applying tensile strain force on said first transistor and said second transistor; and
forming a second stress-producing layer on said first stress-producing layer over said first transistor and said second transistor, said second stress-producing layer applying compressive strain force on said first stress-producing layer, said first transistor, and said second transistor.
12. The method according to claim 11 , said forming of said transistors comprising forming said first transistor as a negative-type (N-type) transistor and said second transistor as a positive-type (P-type) transistor.
13. The method according to claim 12 , said forming of said transistors comprising forming said second transistor to have a silicon germanium channel and said first transistor to have a silicon channel free of germanium.
14. The method according to claim 12 , said forming of said transistors comprising forming said first transistor to have a silicon germanium channel and said second transistor to have a gallium arsenide channel.
15. The method according to claim 11 , said forming of said stress-producing layer comprising forming a layer of at least one of silicon-germanium, silicon-nitride, and silicon-carbon.
16. A method of manufacturing an integrated circuit structure, said method comprising:
forming at least one pair of complementary transistors one of on and in a wafer, said pair of complementary transistors comprising a first transistor and a second transistor; and
forming a first stress-producing layer on said first transistor and said second transistor, said first stress-producing layer applying tensile strain force on said first transistor and said second transistor; and
forming a second stress-producing layer on said first stress-producing layer over said first transistor and said second transistor, said second stress-producing layer applying compressive strain force on said first stress-producing layer, said first transistor, and said second transistor,
a difference in thickness between said first stress-producing layer and said second stress-producing layer altering performance of said first transistor and said second transistor.
17. The method according to claim 16 , said forming of said transistors comprising forming said first transistor as a negative-type (N-type) transistor and said second transistor as a positive-type (P-type) transistor.
18. The method according to claim 17 , said forming of said transistors comprising forming said second transistor to have a silicon germanium channel and said first transistor to have a silicon channel free of germanium.
19. The method according to claim 17 , said forming of said transistors comprising forming said first transistor to have a silicon germanium channel and said second transistor to have a gallium arsenide channel.
20. The method according to claim 16 , said forming of said stress-producing layer comprising forming a layer of at least one of silicon-germanium, silicon-nitride, and silicon-carbon.