Solid-state memory management

1. A method comprising:

receiving electrical power from a host device to power a flash memory controller that comprises a voltage monitor and memory and that controls flash memory;

storing data received from the host device in the memory;

performing concurrent multi-channel flash memory controller operations that comprise concurrent multi-channel flash memory controller operations for writing the data from the memory to the flash memory;

receiving a signal from the voltage monitor as being associated with the performed concurrent multi-channel flash memory controller operations and the received electrical power from the host device; and

based at least in part on the received signal, setting a flash memory controller limit for performing subsequent concurrent multi-channel flash memory controller operations wherein the limit is set to avoid resetting of the flash memory responsive to current demand for performing the subsequent concurrent multi-channel flash memory controller operations.

2. The method of claim 1 wherein the receiving receives a signal that indicates a decrease in voltage occurred during the performed concurrent multi-channel flash memory controller operations.

3. The method of claim 1 wherein the concurrent multi-channel flash memory controller operations further comprise one or more memory operations selected from a group consisting of erase operations and read operations.

4. The method of claim 1 further comprising accessing one or more test protocols prior to the performing the concurrent multi-channel flash memory controller operations.

5. The method of claim 1 further comprising accessing a log of flash memory operations prior to the performing the concurrent multi-channel flash memory controller operations.

6. The method of claim 1 wherein the receiving a signal comprises receiving a digital signal representative of a percentage difference between an acceptable voltage and an unacceptable voltage.

7. The method of claim 1 further comprising repeating the method responsive to an event.

8. The method of claim 7 wherein the event comprises a flash memory reset event.

9. The method of claim 7 wherein the event comprises a timed event.

10. A system comprising:

a power supply interface that receives power from a host device;

a data interface that receives data from the host device and that transmits of data to the host device;

a voltage monitoring circuit that monitors a power supply voltage based on power supplied by the host device via the power supply interface;

multiple channels that controls flash memory; and

control circuitry that requests concurrent flash memory operations via the multiple channels, that monitors the power supply voltage via the voltage monitoring circuit during the request and that sets a limit for subsequent concurrent flash memory operations requests via the multiple channels based at least on the monitored power supply voltage wherein the control circuitry that sets a limit comprises control circuitry that sets a limit that avoids a flash memory reset operation responsive to a current drain caused by the concurrent flash memory operations via the multiple channels.

11. The system of claim 10 wherein the control circuitry that requests concurrent flash memory operations via the multiple channels comprises control circuitry that requests one or more types of operations selected from a group consisting of erase operations, write operations and read operations.

12. The system of claim 10 wherein the control circuitry that sets a limit comprises control circuitry that sets a limit responsive to a decrease in power supply voltage.

13. One or more non-transitory computer-readable storage media comprising processor-executable solid-state drive controller firmware instructions to instruct a processor of a solid-state drive controller wherein the instructions comprise instructions:

to control concurrent multi-channel flash memory operations;

to receive a signal from a voltage monitor of the solid-state drive controller as being associated with the controlled concurrent multi-channel flash memory operations and power supplied via a power supply interface of the solid-state drive controller;

based at least in part on the received signal, to set a limit for control of subsequent concurrent multi-channel flash memory operations wherein the limit is set to avoid resetting of flash memory responsive to current demand for performing the subsequent concurrent multi-channel flash memory controller operations; and

to update the limit in response to a change in power state at the power supply interface of the solid-state drive controller.