Method of read-set and write-set management by distinguishing between shared and non-shared memory regions
A method of read-set and write-set management distinguishes between shared and non-shared memory regions. A shared memory region, used by a transactional memory application, which may be shared by one or more concurrent transactions is identified. A non-shared memory region, used by the transactional memory application, which is not shared by the one or more concurrent transactions is identified. A subset of a read-set and a write-set that access the shared memory region is checked for conflicts with the one or more concurrent transactions at a first granularity. A subset of the read-set and the write-set that access the non-shared memory region is checked for conflicts with the one or more concurrent transactions at a second granularity. The first granularity is finer than the second granularity.
1. A method of read-set and write-set management by distinguishing between shared and non-shared memory regions comprising:
identifying a shared memory region used by a transactional memory application which may be shared by one or more concurrent transactions;
identifying a non-shared memory region used by the transactional memory application which is not shared by the one or more concurrent transactions;
checking a subset of a read-set and a write-set that access the shared memory region for conflicts with the one or more concurrent transactions at a first granularity;
checking a subset of the read-set and the write-set that access the non-shared memory region for conflicts with the one or more concurrent transactions at a second granularity,
wherein the first granularity is finer than the second granularity.
2. The method of claim 1 , wherein the first granularity is word granularity and the second granularity is page granularity.
3. A method of read-set and write-set management by distinguishing between shared and non-shared memory regions comprising:
determining, upon execution of a load instruction as part of a transaction, whether the load instruction reads from a shared region of memory that may be shared by one or more concurrent transactions by comparing the load address to information provided by a shared-region instruction previously executed as part of the transaction;
recording, if the load address is within the shared region of memory, the load address within a Shared Region Load Address Buffer;
recording, if the load address is not within the shared region of memory, the load address within a Non-Shared Region Load Address Buffer;
determining, upon execution of a store instruction as part of the transaction, whether the store instruction writes to the shared region of memory by comparing the store address to information provided by the shared-region instruction;
recording, if the store address is within the shared region of memory, the store address within a Shared Region Store Address Buffer;
recording, if the store address is not within the shared region of memory, the store address within a Non-Shared Region Store Address Buffer;
wherein the Shared Region Load Address Buffer and the Shared Region Store Address Buffer are checked for conflicts with the one or more concurrent transactions at a first granularity,
wherein the Non-Shared Region Load Address Buffer and the Non-Shared Region Store Address Buffer are checked for conflicts with the one or more concurrent transactions at a second granularity, and
wherein the first granularity is finer than the second granularity.
4. The method of claim 3 , wherein the shared-region instruction specifies a start address of the shared memory region and a size of the shared memory region.
5. The method of claim 3 , wherein the first granularity is word granularity and the second granularity is page granularity.
6. The method of claim 3 , wherein the Shared Region Load Address Buffer is a content addressable memory.
7. The method of claim 3 , wherein the Non-Shared Region Load Address Buffer is a content addressable memory.
8. The method of claim 3 , wherein the Non-Shared Region Load Address Buffer is a set associative memory.
9. The method of claim 3 , wherein the Shared Region Store Address Buffer is a content addressable memory.
10. The method of claim 3 , wherein the Non-Shared Region Store Address Buffer is a content addressable memory.
11. The method of claim 3 , wherein the Non-Shared Region Store Address Buffer is a set associative memory.
12. The method of claim 3 , wherein the read-set of the shared memory region is tracked by a shared signature and the read-set of the non-shared memory region is tracked by a non-shared signature.
13. The method of claim 12 , wherein the shared signature is different from the non-shared signature.
14. The method of claim 13 , wherein the shared signature and the non-shared signature are optimized based on the knowledge of whether they refer to shared or non-shared memory regions.
15. A system comprising:
a PCB;
an input device;
an output device;
a storage device; and
a processor comprising one or more cores, each core comprising:
a Shared Region Load Address Buffer,
a Non-Shared Region Load Address Buffer,
a Shared Region Store Address Buffer, and
a Non-Shared Region Store Address Buffer,
wherein the processor's instruction set architecture includes a shared-region instruction,
wherein the processor executes instructions comprising a transactional memory application,
wherein, during execution of the transactional memory application, the processor is configured to perform the following:
determining, upon execution of a load instruction as part of a transaction, whether the load instruction reads from a shared region of memory that may be shared by one or more concurrent transactions by comparing the load address to information provided by a shared-region instruction previously executed as part of the transaction,
recording, if the load address is within the shared region of memory, the load address within a Shared Region Load Address Buffer,
recording, if the load address is not within the shared region of memory, the load address within a Non-Shared Region Load Address Buffer,
determining, upon execution of a store instruction as part of the transaction, whether the store instruction writes to the shared region of memory by comparing the store address to information provided by the shared-region instruction,
recording, if the store address is within the shared region of memory, the store address within a Shared Region Store Address Buffer,
recording, if the store address is not within the shared region of memory, the store address within a Non-Shared Region Store Address Buffer,
wherein the Shared Region Load Address Buffer and the shared region store address buffer are checked for conflicts with the one or more concurrent transactions at a first granularity,
wherein the Non-Shared Region Load Address Buffer and the non-shared region store address buffer are checked for conflicts with the one or more concurrent transactions at a second granularity, and
wherein the first granularity is finer than the second granularity.
16. The system of claim 15 , wherein the shared-region instruction specifies a start address of the shared memory region and a size of the shared memory region.
17. The system of claim 15 , wherein the first granularity is word granularity and the second granularity is page granularity.
18. The system of claim 15 , wherein the Shared Region Load Address Buffer is a content addressable memory.
19. The system of claim 15 , wherein the Non-Shared Region Load Address Buffer is a content addressable memory.
20. The system of claim 15 , wherein the Non-Shared Region Load Address Buffer is a set associative memory.
21. The system of claim 15 , wherein the Shared Region Store Address Buffer is a content addressable memory.
22. The system of claim 15 , wherein the Non-Shared Region Store Address Buffer is a content addressable memory.
23. The system of claim 15 , wherein the Non-Shared Region Store Address Buffer is a set associative memory.