Methods for manufacturing RFID tags and structures formed therefrom

1. A device, comprising:

a) a metal antenna and/or inductor;

b) an interposer attached to said antenna and/or inductor;

c) a dielectric layer on said interposer and/or on at least part of said metal antenna and/or inductor, configured to support integrated circuitry and insulate said integrated circuitry from said interposer and/or said metal antenna and/or inductor;

d) a plurality of diodes and a plurality of thin film transistors on said dielectric layer, said diodes having at least one semiconductor layer in common with said thin film transistors, said at least one semiconductor layer in common with said thin film transistors being formed from a liquid-phase ink comprising silicon; and

e) a plurality of capacitors (i) on or in contact with said dielectric layer and said metal antenna and/or inductor, and (ii) in electrical communication with said metal antenna and/or inductor and at least some of said diodes, said plurality of capacitors having at least one semiconductor layer in common with said plurality of diodes and/or at least one metal layer in common with contacts to said diodes and thin film transistors, said at least one semiconductor layer in common with said plurality of diodes being formed from a same or different liquid-phase ink comprising silicon.

2. The device of claim 1 , wherein said plurality of diodes have at least two different semiconductor layers in common with said plurality of thin film transistors.

3. The device of claim 2 , wherein a first of said at least two different semiconductor layers comprises a lightly doped inorganic semiconductor and a second of said at least two different semiconductor layers comprises a heavily doped inorganic semiconductor.

4. The device of claim 1 , further comprising an interlayer dielectric on or over said plurality of diodes and said plurality of thin film transistors.

5. The device of claim 4 , further comprising a metallization layer over said interlayer dielectric, in electrical communication with said plurality of diodes and said plurality of thin film transistors.

6. The device of claim 5 , wherein said plurality of capacitors have an upper plate comprising said metallization layer.

7. The device of claim 1 , comprising a power conversion block, a logic block, and a memory block, said power conversion block receiving a signal from said metal antenna and/or inductor and comprising a first subset of said diodes and at least a subset of said capacitors, said logic block receiving power from said power conversion block and communicating with said memory block, said logic block comprising a first subset of said thin film transistors, and said memory block comprising a second subset of said diodes and/or a second subset of said thin film transistors.

8. The device of claim 7 , further comprising a clock recovery and/or demodulator block, configured to receive said signal from said metal antenna and/or inductor and comprising a third subset of said diodes and/or a third subset of said thin film transistors.

9. The device of claim 8 , further comprising a modulator block, configured to receive information from said logic block and provide an output signal to said metal antenna and/or inductor, said modulator block comprising a fourth subset of said diodes and/or a fourth subset of said thin film transistors.

10. The device of claim 9 , further comprising an input/output control block or sub-block, configured to receive an input signal from said clock recovery and/or demodulator block and provide said information to said modulator block, said input/output control block or sub-block comprising a fifth subset of said thin film transistors.

11. The device of claim 1 , wherein the device comprises a radio frequency identification (RFID) device.

12. The device of claim 1 , wherein the plurality of thin film transistors is in a first region of the device and the plurality of diodes is in a second region of the device.

13. An integrated circuit comprising:

a) an electrically active substrate;

b) a dielectric layer on the substrate;

c) a plurality of first semiconductor layer elements being formed from a first liquid-phase ink comprising silicon, the plurality of first semiconductor layer elements comprising (i) a thin film transistor channel region in a first region of the substrate, and (ii) a first diode layer element in a second region of the substrate;

d) a plurality of second semiconductor layer elements being formed from a second liquid-phase ink comprising silicon, the plurality of second semiconductor layer elements comprising (i) a second semiconductor layer in the first region of the substrate, and (ii) a second diode layer element in the second region of the substrate; and

e) a plurality of metal elements, the metal elements comprising (i) a metal contact on or over the first semiconductor layer elements and the second semiconductor elements in the first region of the substrate, (ii) a metal gate over the thin film transistor channel region, (iii) a diode contact on or over the first semiconductor layer elements and second semiconductor layer elements in the second region of the substrate, and (iv) an upper capacitor plate in a third region of the substrate, wherein a capacitor comprising the upper capacitor plate is configured to electrically communicate with or be in physical contact with an antenna and/or inductor.

14. The integrated circuit of claim 13 , wherein the substrate comprises a metal foil.

15. The integrated circuit of claim 13 , further comprising the antenna and/or inductor.

16. An integrated circuit comprising:

a) an electrically active substrate;

b) a dielectric layer on the substrate;

c) a plurality of first semiconductor elements being formed from a first liquid-phase ink comprising silicon, the plurality of first semiconductor layer elements comprising (i) a thin film transistor channel region in a first region of the substrate, (ii) a first diode layer element in a second region of the substrate, and (iii) a first capacitor plate in a third region of the substrate;

d) a plurality of second semiconductor layer elements comprising (i) a second semiconductor layer in the first region of the substrate and (ii) a second diode layer element in the second region of the substrate;

e) a plurality of metal elements on or over the first semiconductor layer elements and the second semiconductor layer elements, the metal elements comprising (i) a metal contact in the first region of the substrate, (ii) a metal gate over the thin film transistor channel region, (iii) a diode contact in the second region of the substrate, and (iv) a second capacitor plate in the third region of the substrate; and

f) an antenna and/or inductor in contact with or configured to electrically communicate with a capacitor comprising said first and second capacitor plates.

17. The integrated circuit of claim 16 , wherein the substrate comprises a metal foil.

18. The device of claim 1 , wherein:

said plurality of capacitors has at least one semiconductor layer in common with said plurality of diodes;

the at least one semiconductor layer common to said plurality of diodes and said plurality of thin film transistors comprises a lightly doped inorganic semiconductor; and

the at least one semiconductor layer common to said plurality of diodes and said plurality of capacitors comprises a heavily doped inorganic semiconductor.

19. The integrated circuit of claim 13 , wherein the first region and third region do not overlap.

20. The integrated circuit of claim 19 , wherein the second region is between the first region and the third region.

21. The device of claim 1 , wherein the silicon in each liquid-phase ink comprises one or more silanes.

22. The integrated circuit of claim 13 , wherein the silicon in each liquid-phase ink comprises one or more silanes.

23. The integrated circuit of claim 16 , wherein the silicon in the liquid-phase first ink comprises one or more silanes.