IP Library Granted Patent US 8,994,449
Granted Patent B2
US 8,994,449 · App. 12/690,009 · Granted Mar 31, 2015

Electronic circuit and electronic circuit arrangement

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Quick Facts
Patent No.
US 8,994,449
App. No.
12/690,009
Granted
Mar 31, 2015
Kind
B2
Abstract

In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit.

Claims (78)

1. Electronic cascode circuit, comprising:

a first transistor having a control terminal and first and second controlled terminals, the first controlled terminal of the first transistor coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic cascade circuit;

a second transistor having a control terminal;

a capacitor, wherein a first terminal of the capacitor is coupled to the control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to the first controlled terminal of the first transistor; and

an additional capacitor, wherein a first terminal of the additional capacitor is coupled to the control terminal of the first transistor, and wherein a second terminal of the additional capacitor is coupled to earth potential, the additional capacitor providing capacitive coupling of a gate region associated with the first transistor to the earth potential.

2. Electronic cascode circuit according to claim 1 ,

wherein the first transistor and/or the second transistor are/is configured as field effect transistor or as bipolar transistor.

3. Electronic cascode circuit according to claim 1 ,

wherein the first transistor and/or the second transistor are/is configured as MOS field effect transistor.

4. Electronic cascode circuit according to claim 1 , furthermore comprising:

a substrate;

a first well, doped with dopants of a first conductivity type, in the substrate;

a second well, doped with dopants of a second conductivity type, which is different from the first conductivity type, wherein the second well is arranged in the first well;

wherein the first transistor and the second transistor are arranged in the second well.

5. Electronic cascode circuit according to claim 4 ,

wherein the second terminal of the capacitor is coupled to the well potential of the second well.

6. Electronic cascode circuit according to claim 5 ,

wherein the first conductivity type is an n conductivity type; and

wherein the second conductivity type is a p conductivity type.

7. Electronic cascode circuit according to claim 6 ,

wherein the first transistor and the second transistor are n-channel field effect transistors.

8. Electronic cascode circuit according to claim 4 ,

wherein the first conductivity type is a p conductivity type; and

wherein the second conductivity type is an n conductivity type.

9. Electronic cascode circuit according to claim 8 ,

wherein the first transistor and the second transistor are p-channel field effect transistors.

10. Electronic cascode circuit according to any of claim 4 , furthermore comprising:

a supply potential terminal for applying a supply potential, wherein the supply potential terminal is electrically coupled to the first well.

11. Electronic cascode circuit arrangement, comprising:

a first cascode circuit, which comprises:

a first transistor having a control terminal, and first and second controlled terminals, the first controlled terminal of the first transistor coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic cascade circuit arrangement;

a second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to the a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to the first controlled terminal of the first transistor;

an additional capacitor, wherein a first terminal of the additional capacitor is coupled to the control terminal of the first transistor, and wherein a second terminal of the additional capacitor is coupled to earth potential, the additional capacitor providing capacitive coupling of a gate region associated with the first transistor to the earth potential; and

a second circuit, which is coupled to an input terminal of the first cascode circuit.

12. Electronic cascode circuit arrangement according to claim 11 ,

wherein the second circuit is designed for receiving the radio-frequency input signal.

13. Electronic cascode circuit arrangement according to claim 11 ,

wherein the second circuit has at least one transistor,

wherein a control terminal of the at least one transistor is coupled to the radio-frequency input signal.

14. Electronic cascode circuit arrangement according to claim 11 ,

wherein the second circuit is a second cascode circuit.

15. Electronic cascode circuit arrangement according to claim 14 ,

wherein the second cascode circuit has:

a first transistor;

a second transistor; and

a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical reference potential.

16. Electronic cascode circuit arrangement according to claim 15 ,

wherein the control terminal of the first transistor of the second cascode circuit is coupled to the radio-frequency input signal.

17. Electronic cascode circuit arrangement according to claim 11 ,

wherein the first transistor of the first cascade circuit and/or the second transistor of the first cascode circuit are/is configured as field effect transistor or as bipolar transistor.

18. Electronic cascode circuit arrangement according to claim 15 ,

wherein the first transistor of the second cascode circuit and/or the second transistor of the second cascode circuit are/is configured as field effect transistor or as bipolar transistor.

19. Electronic cascode circuit arrangement according to claim 11 ,

wherein the first transistor of the first cascode circuit and/or the second transistor of the first cascode circuit are/is configured as MOS field effect transistor.

20. Electronic cascode circuit arrangement according to claim 15 ,

wherein the first transistor of the second cascode circuit and/or the second transistor of the second cascode circuit are/is configured as MOS field effect transistor.

21. Electronic cascode circuit arrangement according to claim 11 , furthermore comprising:

a substrate;

a first well, doped with dopants of a first conductivity type, in the substrate;

a second well, doped with dopants of a second conductivity type, which is different from the first conductivity type, wherein the second well is arranged in the first well;

wherein the first transistor of the first cascode circuit and the second transistor of the first cascode circuit are arranged in the second well.

22. Electronic circuit, comprising:

a first transistor having a first controlled terminal coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit;

a second transistor coupled in series with the first transistor;

a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to the first controlled terminal; and

an additional capacitor, wherein a first terminal of the additional capacitor is coupled to a control terminal of the first transistor, and wherein a second terminal of the additional capacitor is coupled to earth potential, the additional capacitor thereby providing capacitive coupling of a gate region associated with the first transistor to the earth potential.

23. Electronic circuit according to claim 22 ,

wherein the first transistor and/or the second transistor are/is configured as MOS field effect transistor.

24. Electronic circuit arrangement, comprising:

a first circuit, which comprises:

a first transistor having a first controlled terminal coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit;

a second transistor coupled in series with the first transistor;

a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to the first controlled terminal of the first transistor;

an additional capacitor, wherein a first terminal of the additional capacitor is coupled to a control terminal of the first transistor, and wherein a second terminal of the additional capacitor is coupled to earth potential, the additional capacitor providing capacitive coupling of a gate region associated with the first transistor to the earth potential; and

a second circuit, which is coupled to an input terminal of the first circuit.

25. The electric circuit arrangement according to claim 24 ,

wherein the additional capacitor is coupled directly to the earth potential.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2010
From: HODEL, UWE; LEUSCHNER, STEPHAN; MUELLER, JAN-ERIK
To: INFINEON TECHNOLOGIES AG
Reel/Frame 024109/0330 →