System for fabricating nanocoils using a wet etch technique
View Patent ↗Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.
1. A system for fabricating nanocoils using a wet etch technique, comprising:
a substrate;
a coiling arm structure including: a buried oxide layer deposited on the substrate;
a stressed coiling bi-layer attached to the buried oxide layer including:
a silicon device layer that includes one or more devices defined thereon;
and a stressed nitride layer that provides a tensile coiling stress; and
a metal encapsulation layer that protects the stressed nitride layer from hydrofluoric (HF) acid used to release the coiling arm structure from the substrate during the wet etch technique so that coiling arm structure coils into nanocoil when released.
2. The system of claim 1 in which the substrate is a silicon substrate.
3. The system of claim 2 in which the silicon substrate is part of a silicon-on-insulator (SOI) wafer.
4. The system of claim 1 in which the buried oxide layer comprises SiO 2 .
5. The system of claim 1 in which silicon device layer includes a memory device.
6. The system of claim 1 in which stressed nitride layer comprises Si 3 Ni 4 .
7. The system of claim 1 in which metal encapsulation layer comprises a Chromium/Gold (Cr/Au) bi-layer.
8. The system of claim 7 in which Cr/Au bi-layer comprises a 100 Å Cr layer and a 100 Å Au layer.
9. The system of claim 1 in which stressed nitride layer is situated on top of silicon device layer.
10. The system of claim 1 in which silicon device layer is situated on top of the stressed nitride layer.