IP Library Granted Patent US 8,432,714
Granted Patent B2
US 8,432,714 · App. 12/694,861 · Granted Apr 30, 2013

Load balancing of parallel connected inverter modules

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,432,714
App. No.
12/694,861
Granted
Apr 30, 2013
Kind
B2
Abstract

A method and an arrangement are disclosed for balancing load between parallel connected inverter modules, which inverter modules are arranged to supply a common load. The method can include providing similar switching instructions for parallel connected inverter modules, determining on the basis of phase currents of each parallel inverter module a first time period for each output phase of each inverter module for correcting current imbalance by advancing or delaying turn-on or turn-off time instants of switch components of the inverter modules, and advancing or delaying the turn-on or turn-off time instants of the switching instructions based on the first time period. The method also can include determining temperatures of each output phase of each inverter module, modifying the switching instructions for one or more of the parallel inverter modules for controlling the temperatures of the output phases, and controlling the inverter modules with a switching instruction in which the turn-on or turn-off times have been advanced or delayed in respect of one or more parallel modules and further modified in respect of one or more inverter modules.

Claims (23)

1. A method of balancing load between parallel connected inverter modules arranged to supply a common load, the method comprising:

providing switching instructions for the parallel connected inverter modules;

determining, based on the phase currents of each parallel inverter module, a first time period for each output phase of each inverter module for correcting current imbalance by advancing or delaying turn-on or turn-off time instants of switch components of the inverter modules;

advancing or delaying the turn-on or turn-off time instants of the switching instructions based on the first time period;

determining temperatures of each output phase of each inverter module;

modifying the switching instructions for at least one of the parallel inverter modules for correcting a temperature imbalance between parallel inverter modules by comparing the temperatures of corresponding output phases of each parallel inverter module with one another, determining, for each output phase of each inverter module, a second time period for correcting a temperature imbalance between output phases of each inverter module based on the comparing, and advancing or delaying the turn-on or turn-off time instant based on a sum of the first time period and the second time period while continuing to operate the inverter modules; and

controlling the inverter modules with the modified switching instructions while continuing to operate the parallel inverter modules;

wherein the first time period has a predetermined maximum value common to each output phase, the method further comprising limiting a maximum value of the first time period based on a value of the second time period.

2. A method according to claim 1 , wherein the comparing of the temperatures of the corresponding output phases comprises:

calculating an average of the temperatures of switches of each phase, the switches of a phase being situated in parallel modules; and

calculating a ratio of the temperature of each switch to the average temperature of the phase in which the switch belongs.

3. A method according to claim 1 , comprising:

determining the first time period using a controller, the controller outputting a value used as the first time period when controlling current imbalance.

4. A method according to claim 1 , comprising:

determining the second time period using a controller, the controller outputting a value used as the first time period when controlling the current imbalance.

5. An arrangement for balancing load between parallel connected inverter modules arranged to supply a common load, the arrangement comprising:

means for providing switching instructions for parallel connected inverter modules;

means for determining, based on phase currents of each parallel inverter module, a first time period for each output phase of each inverter module for correcting current imbalance by advancing or delaying turn-on or turn-off time instants of switch components of the inverter modules;

means for advancing or delaying the turn-on or turn-off time instants of the switching instructions based on the first time period;

means for determining temperatures of each output phase of each parallel inverter module;

means for modifying the switching instructions for at least one of the parallel inverter modules for correcting a temperature imbalance between parallel inverter modules by comparing the temperatures of corresponding output phases of each parallel inverter module with one another, determining, for each output phase of each inverter module, a second time period for correcting a temperature imbalance between output phases of each inverter module based on the comparing, and advancing or delaying the turn-on or turn-off time instant based on a sum of the first time period and the second time period while continuing to operate the inverter modules; and

means for controlling the inverter modules with the modified switching instructions while continuing to operate the inverter modules;

wherein the first time period has a predetermined maximum value common to each output phase, and the maximum value of the first time period is limited based on a value of the second time period.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2018
From: ABB OY
To: ABB SCHWEIZ AG
Reel/Frame 047801/0174 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2010
From: KERONEN, JORMA; VIRTANEN, REIJO; POYHONEN, SIMO
To: ABB OY
Reel/Frame 024232/0834 →