Large-grain crystalline thin-film structures and devices and methods for forming the same
View Patent ↗Methods for forming semiconductor devices include providing a crystalline template having an initial grain size, annealing the crystalline template, the annealed template having a final grain size larger than the initial grain size, forming a buffer layer over the annealed template, and forming a semiconductor layer over the buffer layer.
1. A method for forming a semiconductor device, the method comprising:
providing a cube-textured crystalline template having an initial grain size;
annealing the crystalline template at a temperature above a secondary recrystallization temperature of the crystalline template, the annealed template having a final grain size larger than the initial grain size and comprising one or more grains that are tilted away from (001) by a tilt angle ranging from approximately 15° to approximately 20°;
forming a buffer layer over the annealed template;
forming a substrate layer over the buffer layer;
removing the annealed template to expose a surface of the buffer layer; and
forming a semiconductor layer over the exposed surface of the buffer layer.
2. The method of claim 1 , wherein, before annealing, the crystalline template has an initial crystallographic orientation, and after annealing the annealed template has a final crystallographic orientation different from the initial crystallographic orientation.
3. A method for forming a semiconductor device, the method comprising:
providing a crystalline template having an initial grain size;
annealing the crystalline template, the annealed template having a final grain size larger than the initial grain size and a final crystallographic orientation tilted away from (001) by a tilt angle ranging from approximately 15° to approximately 20°;
forming a buffer layer over the annealed template;
forming a substrate layer over the buffer layer;
removing the annealed template to expose a surface of the buffer layer; and
forming a semiconductor layer over the exposed surface of the buffer layer,
wherein the semiconductor layer has a crystallographic orientation tilted away from (001) by an angle ranging from approximately 2° to approximately 8°.
4. The method of claim 1 , wherein a grain size of the annealed template is greater than approximately 1 cm.
5. The method of claim 1 , further comprising forming a semiconductor device on the semiconductor layer.
6. The method of claim 5 , wherein the semiconductor device comprises at least one polar compound semiconductor material.
7. The method of claim 6 , wherein the semiconductor layer comprises at least one non-polar semiconductor material, and the semiconductor device is substantially free of anti-phase boundaries.
8. The method of claim 1 , wherein the buffer layer comprises at least one of Cr, Pd, Ir, an oxide, or a nitride.
9. The method of claim 1 , wherein the crystalline template comprises at least one of Cu, Ni, or a Cu-Ni alloy.
10. The method of claim 3 , wherein the crystalline template is cube-textured prior to annealing.
11. The method of claim 3 , wherein the crystalline template is annealed at a temperature above a secondary recrystallization temperature of the crystalline template, and the annealed template comprises one or more grains that are not cube-textured.
12. The method of claim 3 , wherein a grain size of the annealed template is greater than approximately 1 cm.
13. The method of claim 3 , further comprising forming a semiconductor device on the semiconductor layer.
14. The method of claim 13 , wherein the semiconductor device comprises at least one polar compound semiconductor material.
15. The method of claim 14 , wherein the semiconductor layer comprises at least one non-polar semiconductor material, and the semiconductor device is substantially free of anti-phase boundaries.
16. The method of claim 3 , wherein the buffer layer comprises at least one of Cr, Pd, Ir, an oxide, or a nitride.
17. The method of claim 3 , wherein the crystalline template comprises at least one of Cu, Ni, or a Cu-Ni alloy.
18. The method of claim 3 , wherein the annealed template comprises only a single grain.
19. The method of claim 3 , wherein a grain size of the annealed template is greater than approximately 10 cm.
20. The method of claim 3 , wherein a grain size of the annealed template is greater than approximately ten times a thickness of the annealed template.
21. The method of claim 1 , wherein the annealed template comprises only a single grain.
22. The method of claim 1 , wherein a grain size of the annealed template is greater than approximately 10 cm.
23. The method of claim 1 , wherein a grain size of the annealed template is greater than approximately ten times a thickness of the annealed template.