Acquisition circuit comprising a buffer capacitor
View Patent ↗The acquisition circuit comprises a second and third electronic switch connected in series between a photodetector and a first input terminal of an amplifier. A reference voltage is applied to a second input terminal of the amplifier, the reference voltage being applied between the photodetector and the second electronic switch by means of a fourth electronic switch. An integration capacitor and a first electronic switch are connected in parallel between the first input terminal and an output terminal of the amplifier. A buffer capacitor is connected between a common terminal of the second and third electronic switches and a secondary voltage. The electrical capacitance of the buffer capacitor is at least equal to that of the integration capacitor.
1. An acquisition circuit comprising:
an amplifier comprising an input terminal and an output terminal,
an integration capacitor and a first switch connected in parallel between the input terminal and the output terminal of the amplifier,
at least two pixels connected to the input terminal, each pixel comprising:
a photodetector,
second and third switches connected in series between the photodetector and the input terminal of the amplifier, wherein the second and third switches have a common terminal,
a buffer capacitor connected to said common terminal, wherein the capacitance of the buffer capacitor is at least equal to that of the integration capacitor,
a fourth switch connected between a reference voltage source and the photodetector.
2. The circuit according to claim 1 , wherein the capacitance of the buffer capacitor is comprised between twice and ten times the capacitance of the integration capacitor.
3. A method for using the device according to claim 1 , wherein during an emission period of a current by the photodetector, a control circuit commanding opening and closing of the switches emits a closing signal of the second switches and an opening signal of the fourth switches.
4. The method according to claim 3 , wherein the time during which the second switches are closed and the fourth switches are simultaneously open is less than a microsecond.
5. The method according to claim 4 , wherein the time during which the second switches are closed and the fourth switches are simultaneously open is comprised between 50 and 100 ns.