Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing

1. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of memory cells arranged in a plurality of rows and 2m columns, and 2m bit lines associated with said 2m columns, respectively, m being a natural number, wherein

each memory cell has a threshold voltage set at any of first to fourth threshold value levels selectively to store any of four different data codes each including first data and second data,

said first threshold value level is lower than a first determination level, said second threshold value level is higher than said first determination level and lower than a second determination level, said third threshold value level is higher than said second determination level and lower than a third determination level, and said fourth threshold value level is higher than said third determination level,

said first to fourth threshold value levels correspond to said four data codes, respectively, rearranged by a procedure corresponding to i) a first step of dividing and rearranging said four data codes in two groups in accordance with whether each data code has said first data having a first logic or a second logic, and ii) a second step of rearranging two data codes of each of said groups in accordance with whether each data code has said second data having said first or second logic,

said data codes corresponding to said first and second threshold value levels, respectively, have said first data of said first logic, and said data codes corresponding said third and fourth threshold value levels, respectively, have said first data of said second logic,

in one of said groups of said data codes having said first data of said first logic, one of said data codes having said second data of said first logic corresponds to a threshold value level lower than the other of said data codes having said second data of said second logic does,

in the other of said groups of said data codes having said first data of said second logic, one of said data codes having said second data of said first logic corresponds to a threshold value level higher than the other of said data codes having said second data of said second logic does, and

said 2m bit lines are previously divided in m bit line groups each of two bit lines;

a cell selection circuit operative in response to an address signal to collectively select 2m of said memory cells of any of said plurality of rows of said memory cell array;

a data read circuit operative in accordance with said first to third determination levels to read 2m data codes from said 2m of said memory cells selected by said cell selection circuit; and

a data output circuit outputting said first and second data of said 2m data codes read by said data read circuit externally from the nonvolatile semiconductor memory device through k output nodes by every k bits, k being a natural number, wherein

said first and second data of each data code are output at different times, respectively, through a single one of said output nodes, wherein said data read circuit performs:

a first step of reading in accordance with said second determination level said first data of a memory sell associated with one bit line of each said bit line group;

a second step of providing said data output circuit with each said first data read in the first step;

a third step of reading in accordance with said second determination level said first data of a memory sell associated with the other bit line of each said bit line group;

a fourth step of providing said data output circuit with each said first data read in the third step;

a fifth step of reading in accordance with said first and third determination levels said second data of a memory sell associated with said one bit line of each said bit line group;

a sixth step of providing said data output circuit with each said second data read in the fifth step;

a seventh step of reading in accordance with said first and third determination levels said second data of a memory sell associated with said other bit line of each said bit line group; and

an eighth step of providing said data output circuit with each said second data read in the seventh step, wherein:

the second and third steps are performed in parallel;

the fourth and fifth steps are performed in parallel; and

the sixth and seventh steps are performed in parallel.

2. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of memory cells arranged in a plurality of rows and 2m columns, and 2m bit lines associated with said 2m columns, respectively, m being a natural number, wherein

each memory cell has a threshold voltage set at any of first to fourth threshold value levels selectively to store any of four different data codes each including first data and second data,

said first threshold value level is lower than a first determination level, said second threshold value level is higher than said first determination level and lower than a second determination level, said third threshold value level is higher than said second determination level and lower than a third determination level, and said fourth threshold value level is higher than said third determination level, and

said 2m bit lines are previously divided in m bit line groups each of two bit lines;

a cell selection circuit operative in response to an address signal to collectively select 2m of said memory cells of any of said plurality of rows of said memory cell array;

a data read circuit operative in accordance with said first to third determination levels to read 2m data codes from said 2m of said memory cells selected by said cell selection circuit; and

a data output circuit outputting said first and second data of said 2m data codes read by said data read circuit externally from the nonvolatile semiconductor memory device through k output nodes by every k bits, k being a natural number, wherein

said first and second data of each data code are output at different times, respectively, through a single one of said output nodes, wherein said data read circuit performs:

a first step of reading said first data of each said memory sell associated with one bit line of each said bit line group;

a second step of providing said data output circuit with each said first data read in the first step;

a third step of reading said first data of each said memory sell associated with the other bit line of each said bit line group;

a fourth step of providing said data output circuit with each said first data read in the third step;

a fifth step of reading said second data of each said memory sell associated with said one bit line of each said bit line group;

a sixth step of providing said data output circuit with each said second data read in the fifth step;

a seventh step of reading said second data of each said memory sell associated with said other bit line of each said bit line group; and

an eighth step of providing said data output circuit with each said second data read in the seventh step, wherein:

the second and third steps are performed in parallel;

the fourth and fifth steps are performed in parallel; and

the sixth and seventh steps are performed in parallel.