IP Library Granted Patent US 8,097,907
Granted Patent B2
US 8,097,907 · App. 12/700,315 · Granted Jan 17, 2012

Solid-state imaging device

Assignee: Unisantis Electronics Singapore Pte Ltd.
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Quick Facts
Patent No.
US 8,097,907
App. No.
12/700,315
Granted
Jan 17, 2012
Kind
B2
Abstract

It is an object to provide an image sensor having a sufficiently-large ratio of a surface area of a light-receiving section to an overall surface area of one pixel. This object is achieved by a solid-state imaging device comprising: a signal line formed on a substrate; an island-shaped semiconductor arranged on the signal line; and a pixel selection line connected to a top of the island-shaped semiconductor, wherein the island-shaped semiconductor includes: a first semiconductor layer formed as a bottom portion of the island-shaped semiconductor and connected to the signal line; a second semiconductor layer formed above and adjacent to the first semiconductor layer; a gate connected to the second semiconductor layer through a dielectric film; a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; and a fourth semiconductor layer formed above and adjacent to the second and third semiconductor layers, and wherein the pixel selection line is comprised of a transparent conductive film, and a part of the gate is disposed inside a depression formed in a sidewall of the second semiconductor layer.

Claims (41)

1. A solid-state imaging device comprising: a signal line formed on a substrate; an island-shaped semiconductor arranged on the signal line; and a pixel selection line connected to a top of the island-shaped semiconductor, wherein the island-shaped semiconductor includes:

a first semiconductor layer formed as a bottom portion of the island-shaped semiconductor and connected to the signal line;

a second semiconductor layer formed above and adjacent to the first semiconductor layer;

a gate connected to the second semiconductor layer through a dielectric film;

a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; and

a fourth semiconductor layer formed above and adjacent to the second and third semiconductor layers,

and wherein:

the pixel selection line is comprised of a transparent conductive film; and

a part of the gate is disposed inside a depression formed in a sidewall of the second semiconductor layer.

2. The solid-state imaging device as defined in claim 1 , wherein:

the signal line is an n+-type diffusion layer;

the first semiconductor layer is an n+-type diffusion layer;

the second semiconductor layer is a p-type impurity-doped region;

the third semiconductor layer is an n-type diffusion layer; and

the fourth semiconductor layer is a p+-type diffusion layer.

3. The solid-state imaging device as defined in claim 2 , wherein:

a combination of the p+-type diffusion layer and the n-type diffusion layer functions as a photoelectric-conversion photodiode;

a combination of the p+-type diffusion layer, the n-type diffusion layer and the p-type impurity-doped region functions as an amplification transistor;

a combination of the n+-type diffusion layer serving as the first semiconductor layer, the p-type impurity-doped region, the n-type diffusion layer and the gate functions as a reset transistor; and

a combination of the p-type impurity-doped region and the n+-type diffusion layer serving as the first semiconductor layer functions as a diode.

4. The solid-state imaging device as defined in claim 1 , wherein the island-shaped semiconductor has a square or rectangular pillar shape.

5. The solid-state imaging device as defined in claim 1 , wherein the island-shaped semiconductor has a hexagonal pillar shape.

6. The solid-state imaging device as defined in claim 1 , wherein the island-shaped semiconductor has a circular pillar shape.

7. A solid-state imaging apparatus comprising a plurality of the solid-state imaging devices as defined in claim 1 , wherein the solid-state imaging devices are arranged in an n-row by m-column array (wherein each of n and m is an integer of 1 or more) with respect to the substrate.

8. A solid-state imaging apparatus comprising a plurality of the solid-state imaging devices as defined in claim 4 , wherein the solid-state imaging devices are arranged in an n-row by m-column array (wherein each of n and m is an integer of 1 or more) with respect to the substrate.

9. A solid-state imaging apparatus comprising a plurality of the solid-state imaging devices as defined in claim 6 , wherein the solid-state imaging devices are arranged in an n-row by m-column array (wherein each of n and m is an integer of 1 or more) with respect to the substrate.

10. A solid-state imaging apparatus comprising a plurality of the solid-state imaging devices as defined in claim 1 , wherein the solid-state imaging devices are arranged on the substrate in a honeycomb pattern.

11. A solid-state imaging apparatus comprising a plurality of the solid-state imaging devices as defined in claim 5 , wherein the solid-state imaging devices are arranged on the substrate in a honeycomb pattern.

12. A solid-state imaging apparatus comprising a plurality of the solid-state imaging devices as defined in claim 6 , wherein the solid-state imaging devices are arranged on the substrate in a honeycomb pattern.

13. A method of producing the solid-state imaging device as defined in claim 1 , comprising the steps of:

forming an oxide film on a silicon substrate;

forming a p-type silicon on the oxide film;

forming an oxide film-based mask and a nitride film-based mask by depositing a nitride film on the p-type silicon, depositing an oxide film on the nitride film, forming a resist for a silicon pillar, etching the oxide film and the nitride film, and removing the resist;

forming the depression in the sidewall of the p-type impurity-doped region by etching the p-type silicon to form a silicon pillar, depositing a nitride film, etching the nitride film in such a manner that a sidewall-shaped nitride film is left on a sidewall of the silicon pillar, and isotropically etching the p-type silicon;

forming the island-shaped semiconductor having the depression in the sidewall of the p-type impurity-doped region by etching the p-type silicon;

forming the n+-type diffusion layer of the island-shaped semiconductor, and the signal line, by forming an oxide film to prevent ion channeling during ion implantation, forming a continuous n+-type diffusion layer through phosphorus implantation and annealing, forming a resist for the signal line, and etching the oxide film and the silicon;

after removing the resist, the sidewall-shaped nitride film and the oxide film, forming the gate by depositing an oxide film, subjecting the oxide film to flattening and etching-back, forming a gate dielectric film, depositing polysilicon, subjecting the polysilicon to flattening and etching-back, forming a resist for the gate, and etching the polysilicon;

after removing the resist, forming the charge storage section through phosphorus implantation;

forming the p+-type diffusion layer by depositing an oxide film, subjecting the oxide film to flattening and etching-back, removing the nitride film-based mask, forming an oxide film, and performing boron implantation and annealing;

after removing the oxide film, forming the pixel selection line by depositing a transparent conductive film, forming a resist for the pixel selection line, etching the transparent conductive film, and removing the resist; and

forming a surface protection film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2011
From: UNISANTIS ELECTRONICS JAPAN LTD.
To: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.
Reel/Frame 026970/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2010
From: MASUOKA, FUJIO; NAKAMURA, HIROKI
To: UNISANTIS ELECTRONICS (JAPAN) LTD.
Reel/Frame 023901/0965 →
Priority Claims (1)
WO PCT/JP2008/058412 · May 2, 2008 · international
Continuity (3)
Continuation PCTJP2009058629 · May 7, 2009
Provisional Application 61207552 · Feb 13, 2009
Related Publication 20100219457A1 · Sep 2, 2010