Techniques for enabling simplified LDPC encoding and decoding
A method for low density parity check (LDPC) encoding comprises concatenating a predetermined number of zero bits to a scrambled input data word to generate a concatenated binary sequence; computing parity bits to be added to the concatenated binary sequence, wherein the computing is performed using an LDPC encoder; producing an encoded codeword that consists of the concatenated binary sequence and the parity bits; and replacing the predetermined number of zero bits in the encoded codeword with a scrambled binary sequence, thereby discarding the zero bits.
1. A single-carrier transmitter, comprising:
a scrambler for scrambling an input data word,
a zero padding unit for concatenating a predetermined number of zero bits to the scrambled input data word;
a low density parity check (LDPC) encoder for generating an encoded codeword that consists of the scrambled input data word, the predetermined number of zero bits and parity bits;
a linear feedback shift register (LFSR) for replacing the predetermined number of zero bits in the encoded codeword with a binary scrambled sequence; and
a modulator for modulating a modified encoded codeword that consists of scrambled input data word, a scrambled binary sequence, and the parity bits on a single carrier signal.
2. The transmitter of claim 1 , wherein the length of a LDPC code of the LDPC encoder is N.
3. The transmitter of claim 2 , wherein the input data word is in a length of N/4, the predetermined number of zero bits is N/4, the number of parity bits is N/2, and the encoded codeword is in a length of N.
4. The transmitter of claim 3 , wherein the parameter N equals to 672.
5. The transmitter of claim 1 , wherein a rate of the LDPC encoder is ½.
6. The transmitter of claim 1 , wherein replacing the predetermined number of zero bits with the scrambled binary sequence, further comprises:
performing a logical XOR operation between bits of the scrambled input data word and a polynomial sequence generated by the LFSR.
7. The transmitter of claim 1 , wherein modulator is any of a phase-shift keying (BPSK) modulator, a Quadrature phase-shift keying (QPSK) modulator, and a differential phase-shift keying (DPSK) modulator.
8. A method for low density parity check (LDPC) encoding, comprising:
concatenating a predetermined number of zero bits to a scrambled input data word to generate a concatenated binary sequence;
computing parity bits to be added to the concatenated binary sequence, wherein the computing is performed using an LDPC encoder;
producing an encoded codeword that consists of the concatenated binary sequence and the parity bits; and
replacing the predetermined number of zero bits in the encoded codeword with a scrambled binary sequence, thereby discarding the zero bits.
9. The method of claim 8 , wherein a length of a LDPC code of the LDPC encoder is N.
10. The method of claim 9 , wherein the scrambled input data word is in a length of N/4, the predetermined number of zero bits is N/4, the number of parity bits is N/2, and the encoded codeword is in a length of N.
11. The method of claim 10 , wherein the parameter N equals to 672.
12. The method of claim 8 , wherein a rate of the LDPC encoder is %.
13. The method of claim 8 , wherein replacing the predetermined number of zero bits with the binary scrambled sequence, further comprises:
performing a logic XOR function between bits of the scrambled input data word and a polynomial sequence generated by a linear feedback shift register (LFSR).
14. A single-carrier receiver, comprising:
a demodulator for demodulating a received wireless signal to extract a transmitted encoded codeword, wherein the encoded codeword consists of a scrambled input data word, a scrambled binary sequence, and parity bits;
a linear feedback shift register (LFSR) for descrambling the binary scrambled sequence;
a maximum ratio combining (MRC) unit for combining the descrambled scrambled binary sequence and the scrambled input data word; and
an LDPC decoder for decoding an input codeword that consists of a combined binary sequence generated by the MRC unit, a predetermined number of zero bits, and the parity bits, wherein the low density parity check (LDPC) decoder outputs a decoded input data word.
15. The single-carrier receiver of claim 14 , further comprises:
a descrambler for descrambling the decoded input data word; and
an error checking unit for detecting and correcting errors in the descrambled decoded input data word.
16. The single-carrier receiver of claim 15 , wherein a length of a LDPC code of the LDPC decoder is N.
17. The single-carrier receiver of claim 16 , wherein the combined binary sequence is in a length of N/4, the predetermined number of zero bits is N/4, the number of parity bits is N/2, and the decoded input data word is in a length of N/4.
18. The single-carrier receiver of claim 17 , wherein the parameter N equals to 672.
19. The single-carrier receiver of claim 15 , wherein a rate of the LDPC decoder is ½.