Memory circuit including row and column selection for writing information

1. A memory circuit for writing information into a memory cell selected by selecting a column and a row of the memory cell, the memory circuit comprising:

memory cells A arranged in columns and rows;

memory cells B for storing information indicative of whether writing into the memory cells A of the each of the rows has been completed or not, where an associated memory cell B is provided for each of the rows; and

a logic circuit for selecting one of the rows of memory cells A by utilizing the information stored in one of the memory cells B,

wherein the memory circuit is configured to:

write the information indicative of a completion of a writing into a selected row of memory cells A into an associated memory cell B upon the completion of writing into the selected row of memory cells A by action of the logic circuit to send an output voltage change of the associated memory cell B to a bit line of the selected row and to a bit line of a second row of memory cells A, such that the selected row is switched from a selected state to a non-selected state, and the second row of memory cells A is switched from the non-selected state to the selected state to enable writing of the second row of memory cells A; and

repeat writing into additional associated memory cells B to thereby sequentially select additional rows of memory cells A for writing information.

2. The memory circuit according to claim 1 , wherein the memory circuit has an erroneous write prevention function utilizing the information stored in the memory cells B.

3. The memory circuit according to claim 1 , wherein the additional associated memory cells B of neighboring rows are arranged in different columns and connected to a corresponding column by a bit-line connection.

4. The memory circuit according to claim 1 , wherein a delay time period is provided between a change occurring in the information stored in the associated memory cell B and a change occurring in a row selection signal.

5. The memory circuit according to claim 1 , further comprising a column decoder constituted from an analog-digital converter.

6. The memory circuit according to claim 5 , wherein:

the column decoder comprising the analog-digital converter has word lines extending therefrom, the word lines corresponding to an output of the column decoder; and

each of the word lines is provided with one of a pull-up function and a pull-down function.

7. The memory circuit according to claim 5 , further comprising a function of cutting off current flowing through the analog-digital converter.

8. The memory circuit according to claim 1 , further comprising a latch circuit, wherein the memory circuit includes:

a function of causing the latch circuit to read and hold information from the memory cells A and information from the memory cells B; and

a function of cutting off current flowing through the memory cells A and the memory cells B.

9. The memory circuit according to claim 1 , further comprising a memory cell C that is provided before a first row of the memory cells A, and wherein the memory circuit controls whether to enable or disable writing into the memory cells A of the first row based on stored information of the memory cell C.

10. The memory circuit according to claim 1 , further comprising a fuse capable of being electrically blown, as an element for storing information.

11. The memory circuit according to claim 5 , wherein the memory circuit is formed on a semiconductor chip having a circuit for generating a reference potential, and wherein the reference potential is used in common by the analog-digital converter.

12. The memory circuit according to claim 1 , wherein the logic circuit comprises an NOR gate and an inverter coupled to the associated memory cell.