Deep trench capacitor on backside of a semiconductor substrate
View Patent ↗A pair of through substrate vias is formed through a stack including a lightly doped semiconductor and a bottom semiconductor layer in a semiconductor substrate. The top semiconductor layer includes semiconductor devices such as field effect transistors. At least one deep trench is formed on the backside of the semiconductor substrate in the bottom semiconductor layer and at least one dielectric layer thereupon. A node dielectric and a conductive inner electrode are formed in each of the at least one deep trench. Substrate contact vias abutting the bottom semiconductor layer are also formed in the at least one dielectric layer. Conductive wiring structures on the backside of the semiconductor substrate provide lateral connection between the through substrate vias and the at least one conductive inner electrode and the substrate contact vias.
1. A semiconductor structure comprising:
at least one semiconductor device located directly on a front side surface of a semiconductor substrate;
a trench capacitor located directly on a backside surface of said semiconductor substrate and comprising a conductive inner electrode, a node dielectric, and a bottom semiconductor layer having a dopant concentration of 1.0×10 18 /cm 3 or greater; and
a pair of through-substrate vias electrically connecting said conductive inner electrode and said bottom semiconductor layer to said at least one semiconductor device.
2. The semiconductor structure of claim 1 , further comprising a top semiconductor layer having a dopant concentration less than 1.0×10 18 /cm 3 and located directly underneath said front side surface of said semiconductor substrate, wherein said at least one semiconductor device is located directly on said top semiconductor layer.
3. The semiconductor structure of claim 2 , wherein an entirety of said top semiconductor layer is single crystalline and wherein an entirety of said bottom semiconductor layer is single crystalline.
4. The semiconductor structure of claim 2 , further comprising:
a front side dielectric layer located directly on said front side surface;
a pair of metal interconnect structures embedded in said dielectric layer and abutting said at least one semiconductor device and said pair of through-substrate vias; and
a pair of dielectric liners extending from said front side dielectric layer through said top semiconductor layer and said bottom semiconductor layer and to said backside surface and laterally abutting and surrounding said pair of through-substrate vias.
5. The semiconductor structure of claim 1 , further comprising:
at least one backside dielectric layer abutting said backside surface; and
an array of substrate contact vias embedded in said at least one backside dielectric layer and vertically abutting said bottom semiconductor layer.
6. The semiconductor structure of claim 5 , further comprising:
a first conductive wiring structure abutting said array of substrate contact vias and electrically connected to one of said pair of through-substrate vias; and
a second conductive wiring structure abutting said conductive inner electrode and electrically connected to the other of said pair of through-substrate vias.
7. The semiconductor structure of claim 1 , wherein said node dielectric comprises silicon nitride, silicon oxide, silicon oxynitride, a dielectric metal oxide, a dielectric metal nitride, a dielectric metal oxynitride, a silicate alloy of a dielectric metal oxide, a silicate alloy of a dielectric metal nitride, a silicate alloy of a dielectric metal oxynitride, or an alloy or mixture thereof.
8. The semiconductor structure of claim 1 , wherein said conductive inner electrode comprises a doped semiconductor material, a metal, a conductive metal nitride, or a combination thereof.
9. The semiconductor structure of claim 1 , wherein said semiconductor substrate is a semiconductor-on-insulator (SOI) substrate including a buried insulator layer vertically abutting said top semiconductor layer and said bottom semiconductor layer.
10. The semiconductor structure of claim 9 , wherein said node dielectric vertically abuts said buried insulator layer.
11. The semiconductor structure of claim 1 , wherein said semiconductor substrate is a bulk substrate wherein said top semiconductor layer vertically abuts said bottom semiconductor layer.
12. The semiconductor structure of claim 1 , wherein said at least one semiconductor device includes a field effect transistor.
13. A method of forming a semiconductor structure comprising:
forming at least one semiconductor device directly on a front side surface of a semiconductor substrate;
forming a pair of through-substrate vias extending at least from said front side surface of said semiconductor substrate to a backside surface of said semiconductor substrate; and
forming a trench capacitor directly on said backside surface of said semiconductor substrate, wherein said trench capacitor comprises a conductive inner electrode, a node dielectric, and a bottom semiconductor layer having a dopant concentration of 1.0×10 18 /cm 3 or greater, wherein said pair of through-substrate vias provide electrical connection between said at least one semiconductor device and conductive inner electrode and said bottom semiconductor layer.
14. The method of claim 13 , wherein said semiconductor substrate includes a top semiconductor layer having a dopant concentration less than 1.0×10 18 /cm 3 and located directly underneath said front side surface of said semiconductor substrate, and wherein said at least one semiconductor device is located directly on said top semiconductor layer.
15. The method of claim 14 , further comprising:
forming a front side dielectric layer directly on said front side surface;
forming a pair of metal interconnect structures in said dielectric layer, wherein said pair of metal interconnect structures abut said at least one semiconductor device and said pair of through-substrate vias; and
forming a pair of dielectric liners extending from said front side dielectric layer through said top semiconductor layer and said bottom semiconductor layer and to said backside surface, wherein said pair of dielectric liners laterally abuts and surrounds said pair of through-substrate vias.
16. The method of claim 13 , further comprising:
forming at least one backside dielectric layer directly on backside surface; and
forming an array of substrate contact vias in said at least one backside dielectric layer and directly on said bottom semiconductor layer.
17. The method of claim 16 , further comprising:
forming a first conductive wiring structure directly on said array of substrate contact vias, wherein said first conductive wiring structure is electrically connected to one of said pair of through-substrate vias; and
forming a second conductive wiring structure directly on said conductive inner electrode, wherein said second conductive wiring structure is electrically connected the other of said pair of through-substrate vias.
18. The method of claim 13 , wherein said semiconductor substrate is a semiconductor-on-insulator (SOI) substrate including a buried insulator layer vertically abutting said top semiconductor layer and said bottom semiconductor layer.
19. The method of claim 18 , wherein said node dielectric vertically abuts said buried insulator layer.
20. The method of claim 13 , wherein said semiconductor substrate is a bulk substrate wherein said top semiconductor layer vertically abuts said bottom semiconductor layer.