Method and system for symmetric transmit and receive latencies in an energy efficient PHY
View Patent ↗Aspects of a method and system for symmetric transmit and receive latencies in an energy efficient PHY are provided. In this regard, a delay introduced by a PHY of a network device for outbound traffic and a delay introduced by the PHY for inbound traffic may be controlled such that a transmit delay of the network device is equal, within a tolerance, to a receive latency of the network device. The delays may be controlled based on whether one or more energy efficiency features are enabled in the PHY. The delay introduced by the PHY for outbound traffic may be controlled based on an amount of buffered inbound traffic. The delay introduced by the PHY for inbound traffic may be controlled based on an amount of buffered outbound traffic. The delays may be controlled such that said receive latency and the transmit latency are approximately constant regardless of a mode of operation of the network device.
1. A method for networking, the method comprising:
performing by one or more circuits and/or processors in a network device:
controlling, based on whether one or more energy efficient networking features are enabled in a physical layer device (PHY) of said network device, at least one of a delay introduced by a transmit path in said PHY for outbound traffic and a delay introduced by a receive path in said PHY for inbound traffic such that a transmit latency of said transmit path in said network device is substantially equal to a receive latency of said receive path in said network device.
2. The method according to claim 1 , wherein said energy efficient network features comprise low power idle and sub-rating.
3. The method according to claim 1 , comprising controlling said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic by controlling one or more of:
a size of one or more buffers;
one or more thresholds of said one or more buffers; and
a rate at which data is read out of said one or more buffers.
4. The method according to claim 1 , comprising controlling said delay introduced by said PHY for said outbound traffic based on an amount of buffered inbound traffic.
5. The method according to claim 1 , comprising controlling said delay introduced by said PHY for said inbound traffic based on an amount of buffered outbound traffic.
6. The method according to claim 1 , comprising controlling said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic based on a type of traffic being communicated by said network device.
7. The method according to claim 1 , comprising controlling said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic based on traffic patterns into and/or out of said PHY.
8. The method according to claim 1 , wherein said PHY is an Ethernet PHY.
9. The method according to claim 1 , comprising controlling said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic such that said receive latency and said transmit latency are approximately constant regardless of a mode of operation of said network device.
10. A system for networking, the system comprising:
one or more circuits and/or processors for use in a network device, wherein the one or more circuits and/or processors are operable to:
controlling, based on whether one or more energy efficient networking features are enabled in a physical layer device (PHY) of said network device, at least one of a delay introduced by a transmit path in said PHY for outbound traffic and a delay introduced by a receive path in said PHY for inbound traffic such that a transmit latency of said transmit path in said network device is substantially equal to a receive latency of said receive path in said network device.
11. The system according to claim 10 , wherein said energy efficient network features comprise low power idle and sub-rating.
12. The system according to claim 10 , wherein said one or more circuits and/or processors are operable to control said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic by controlling one or more of:
a size of one or more buffers;
one or more thresholds of said one or more buffers; and
a rate at which data is read out of said one or more buffers.
13. The system according to claim 10 , wherein said one or more circuits and/or processors are operable to control said delay introduced by said PHY for said outbound traffic based on an amount of buffered inbound traffic.
14. The system according to claim 10 , wherein said one or more circuits and/or processors are operable to control said delay introduced by said PHY for said inbound traffic based on an amount of buffered outbound traffic.
15. The system according to claim 10 , wherein said one or more circuits and/or processors are operable to control said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic based on a type of traffic being communicated by said network device.
16. The system according to claim 10 , wherein said one or more circuits and/or processors are operable to control said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic based on traffic patterns into and/or out of said PHY.
17. The system according to claim 10 , wherein said PHY is an Ethernet PHY.
18. The system according to claim 10 , wherein said one or more circuits and/or processors are operable to control said delay introduced by said PHY for said outbound traffic and said delay introduced by said PHY for said inbound traffic such that said receive latency and said transmit latency are approximately constant regardless of a mode of operation of said network device.