IP Library Granted Patent US 7,951,645
Granted Patent B2
US 7,951,645 · App. 12/702,615 · Granted May 31, 2011

Power module for low thermal resistance and method of fabricating the same

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Quick Facts
Patent No.
US 7,951,645
App. No.
12/702,615
Granted
May 31, 2011
Kind
B2
Abstract

A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Claims (12)

1. A method of fabricating a power module for low thermal resistance, the method comprising:

forming an adhesive layer on a substrate using a thermally conductive adhesive;

forming a device layer comprising a power device, a passive device, and a support tab on the adhesive layer;

forming wiring for each of the power device and the passive device in the device layer;

forming a sealing material hermetically sealing the device layer.

2. The method of claim 1 , wherein the device layer is formed using a pick-and-place machine.

3. The method of claim 1 , wherein the sealing material is formed using transfer molding.

4. The method of claim 1 , wherein the support tab is placed between the support pin and the substrate and buffers a stress induced by the support pin virtually always prevents the substrate from breaking.

5. The method of claim 1 , wherein the support tab is formed using a material which acts as a buffer against a mechanical stress induced by the support pin on the substrate.

6. The method of claim 5 , wherein the support tab is formed using a ductile metal.

7. The method of claim 1 , wherein the substrate is formed with a lower copper layer, a ceramic layer, and an upper copper layer and the ceramic layer is formed from at least one material selected from the group consisting of aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), beryllium oxide (BeO), and silicon nitride (SiN).

8. The method of claim 1 , wherein the adhesive layer is formed using solder and screen printing.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →