Method of fabricating gate configurations for an improved contacts in nanowire based electronic devices

1. A method for fabricating an electronic device, comprising:

(a) providing a nanowire having a semiconductor inner portion, an insulating shell layer surrounding the core, and a conductive layer surrounding the insulating shell layer;

(b) removing the conductive layer from the nanowire except for a first portion of the conductive layer at least partially encircling the nanowire at a first location along the length of the nanowire and at least a second portion of the conductive layer along a length of the nanowire on a side opposite from the removing;

(c) positioning a dielectric material on the nanowire;

(d) removing the dielectric material and the insulating shell layer from the nanowire at a second location and a third location along the length of the nanowire, wherein the second location and the third location are on opposite respective sides of the first location along the length of the nanowire, wherein at least one of the second location and the third location overlaps with the second portion of the conductive layer along the length of the nanowire; and

(e) forming a source contact on the second location and a drain contact on the third location.

2. The method of claim 1 , further comprising:

positioning the nanowire on a substrate prior to step (b).

3. The method of claim 1 , wherein step (d) further comprises:

removing a portion of the diameter of the semiconductor inner portion from the nanowire at the second and third locations.

4. The method of claim 3 , wherein step (d) comprises:

applying a photoresist material to the nanowire at least at the first location;

using etching to remove the dielectric material, the insulating shell layer, and a portion of the diameter of the semiconductor inner portion from the nanowire at the second and third locations.

5. The method of claim 3 , wherein the removing of step (d) comprises:

planarizing the dielectric material, the insulating shell layer, and a portion of the semiconductor inner portion from the nanowire at the second and third locations.

6. The method of claim 1 , wherein the semiconductor inner portion is a semiconductor core.

7. The method of claim 1 , further comprising:

depositing the nanowire on a substrate prior to step (b).

8. The method of claim 1 , wherein the nanowire is one of a plurality of nanowires deposited on the substrate, each nanowire having a semiconductor inner portion, an insulating shell layer surrounding the core, and a conductive layer surrounding the insulating shell layer;

wherein steps (b)-(e) are performed on the plurality of nanowires to form the electronic device.

9. The method of claim 8 , wherein two or more of the plurality of nanowires share a common source contact and/or drain contact.

10. The method of claim 8 , further comprising:

coupling the conductive layers of two or more of the plurality of nanowires.

11. The method of claim 1 , wherein step (b) comprises:

applying a photoresist material to the nanowire at least at the first location; and

using etching to remove the conductive layer from the nanowire except for at the first portion and the second portion of the conductive layer.

12. The method of claim 1 , wherein step (d) comprises:

applying a photoresist material to the nanowire at least at the first location;

using etching to remove the dielectric material and the insulating shell layer from the nanowire at the second and third locations.

13. The method of claim 1 , wherein the removing of step (b) and/or step (d) comprises:

using reactive ion etching.

14. The method of claim 13 , wherein said using reactive ion etching comprises:

tuning at least one of a plasma power, plasma pressure, etching gas composition, and substrate bias to adjust an ion beam.

15. The method of claim 1 , wherein the positioning a dielectric material on the nanowire of step (c) comprises:

using vapor deposition.

16. The method of claim 1 , wherein the positioning a dielectric material on the nanowire of step (c) comprises at least one of using a spin-on glass process, using a spin-on polymer process, and applying perelyne.

17. The method of claim 1 , wherein the removing of step (b) and/or step (d) comprises:

using plasma dry etching.

18. The method of claim 17 , wherein said using plasma dry etching comprises:

tuning at least one of a gas ratio and a gas pressure to control etching.

19. The method of claim 1 , wherein step (e) comprises:

metallizing the second location and the third location to form the drain contact and source contact, respectively.

20. The method of claim 1 , further comprising:

prior to step (e), doping the semiconductor inner portion at the second location and/or the third location.

21. A method for fabricating an electronic device, comprising:

(a) providing a nanowire having a semiconductor inner portion, an insulating shell layer surrounding the core, and a conductive layer surrounding the insulating shell layer;

(b) selectively removing the conductive layer from the nanowire except for a first portion of the conductive layer at least partially encircling the nanowire at a first location along the length of the nanowire and at least a second portion of the conductive layer along a length of the nanowire on a side opposite from the removing;

(c) removing the insulating shell layer from the nanowire at a second location and a third location along the length of the nanowire, wherein the second location and the third location are on opposite respective sides of the first location, wherein at least one of the second location and the third location overlaps with the second portion of the conductive layer along the length of the nanowire; and

(e) forming a source contact on the second location and a drain contact on the third location.