IP Library Granted Patent US 8,497,964
Granted Patent B2
US 8,497,964 · App. 12/703,315 · Granted Jul 30, 2013

TFT-LCD array substrate

Inventors: Xu Chen (Beijing, CN); Seung Moo Rim (Beijing, CN); Zhenyu Xie (Beijing, CN); Xiang Liu (Beijing, CN)
Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
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Quick Facts
Patent No.
US 8,497,964
App. No.
12/703,315
Granted
Jul 30, 2013
Kind
B2
Abstract

A thin film transistor liquid crystal display (TFT-LCD) array substrate and a method for forming the same. The thin film transistor liquid crystal display (TFT-LCD) device, comprising gate lines and data lines that intersecting with each other to define pixel regions, wherein a pixel electrode and a thin film transistor are formed in each of the pixel regions, and wherein the data lines each have a mirror-symmetry structure so that coupling capacitance between one data line and the pixel electrodes in an upper adjacent pixel region and a lower pixel region that are adjacent changes oppositely.

Claims (9)

1. An array substrate for a thin film transistor liquid crystal display (TFT-LCD) device, comprising gate lines and data lines that intersecting with each other to define pixel regions, wherein a pixel electrode and a thin film transistor are formed in each of the pixel regions, and wherein the data lines each have an S-shaped structure so that coupling capacitance between one data line and the pixel electrodes in an upper adjacent pixel region and a lower pixel region that are adjacent changes oppositely;

wherein each data line comprises data stripes and connecting stripes connected with the data stripes, data stripes intersect with the gate lines, and as for the upper and lower adjacent pixel regions in one pixel column, the data stripe located at a left side of the upper pixel region is connected to the data stripe located at a right side of the lower pixel region by the connecting stripe, or the data stripe located at a right side of the upper pixel region is connected to the data stripe located at a left side of the lower pixel region by the connecting stripe;

wherein the connecting stripes comprises a first sub connecting stripe, a second sub connecting stripe and a third sub connecting stripe, and in one pixel region, the second sub connecting stripe serves to connect the first sub connecting stripe to a lower end of one data stripe, and the third sub connecting stripe serves to connect the first sub connecting stripe to an upper end of another data stripe, so that the data line for one pixel column has the S-shaped structure;

wherein the first sub connecting stripe within one pixel region is disposed at a same level as the data stripes and extends parallel to the gate lines, and the second and third sub connecting stripes within the same pixel region are disposed at a same level as the pixel electrodes.

2. The TFT-LCD array substrate of claim 1 , wherein the upper and lower adjacent pixel regions are located in one same pixel column, and wherein the upper pixel region comprises 1-10 sub-pixels and the lower pixel region comprises 1-10 sub-pixels.

3. The TFT-LCD array substrate of claim 1 , wherein as for two upper and lower adjacent pixel regions in one pixel column, the data line is disposed on a side of the pixel electrode in the upper pixel region and on an opposite side of the pixel electrode in the lower pixel region so that the data line for the pixel column has the S-shaped structure.

4. The TFT-LCD array substrate of claim 3 , wherein the upper and lower adjacent pixel regions are located in one same pixel column, and wherein the upper pixel region comprises 1-10 sub-pixels and the lower pixel region comprises 1-10 sub-pixels.

5. The TFT-LCD array substrate of claim 1 , wherein as for the adjacent upper and lower pixel regions, thin film transistors are disposed at one side of sub-pixels in one pixel region and at the other side of sub-pixels in the other pixel region so that the thin film transistors are staggerly provided.

6. The TFT-LCD array substrate of claim 5 , wherein the upper and lower adjacent pixel regions are located in one same pixel column, and wherein the upper pixel region comprises 1-10 sub-pixels and the lower pixel region comprises 1-10 sub-pixels.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2015
From: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD
To: BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO. LTD
Reel/Frame 036644/0601 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2010
From: CHEN, XU; RIM, SEUNG MOO; XIE, ZHENYU; LIU, XIANG
To: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 023919/0923 →
Priority Claims (1)
CN 2009 1 0078446 · Feb 23, 2009 · national
Continuity (1)
Related Publication 20100214518A1 · Aug 26, 2010