Semiconductor device and production method therefor

1. A semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region and a source region of a second MOS transistor, the semiconductor device, comprising:

a substrate;

a dielectric film on the substrate;

a planar semiconductor layer formed on the on-substrate dielectric film,

wherein:

the first MOS transistor includes a first drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed in such a manner that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film; and

the second MOS transistor includes a third drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a fourth source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed in such a manner that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film,

and wherein a first silicide layer is formed to connect at least a part of a surface of the first drain or source region and at least a part of a surface of the third drain or source region and the first silicide layer is also formed in the first drain or source region and the third drain or source region, and in an area on which the first gate electrode, the second gate electrode and the gate line extending from the first gate electrode and second gate electrode are absent.

2. The semiconductor device as defined in claim 1 , wherein the first gate electrode and the second gate electrode are connected through a gate line extending from the first gate electrode and the second gate electrode, wherein a contact formed on the gate line is formed in an area between the first pillar-shaped semiconductor layer and the second pillar-shaped semiconductor layer.

3. The semiconductor device as defined in claim 1 , further comprising a first gate line, integrally formed with the first gate electrode in such a manner that top surfaces of the first gate electrode and the first gate line have a same height and an entire area of the top surface of the integrated combination of the gate electrode and the gate line becomes parallel to the substrate, wherein a contact for the gate electrode is provided in such a manner as to be in contact with the top surface formed parallel to the substrate.

4. The semiconductor device as defined in claim 1 , further comprising a third dielectric film interposed between the first dielectric film and the planar semiconductor layer including the first drain or source region, wherein the first dielectric film is formed beneath the first gate electrode and a gate line extending from the first gate electrode, and the third dielectric film has a thickness larger than that of the first dielectric film.

5. The semiconductor device as defined in claim 1 , wherein one or each of the first and second MOS transistors comprises a plurality of the pillar-shaped semiconductor layers, wherein a single common contact is formed commonly on source or drain regions formed in the upper portion of at least two said pillar-shaped semiconductor layers, the source or drain regions being connected to each other through the single common contact.

6. The semiconductor device as defined in claim 1 , wherein the second source or drain region and the first gate electrode are connected through a single common contact.

7. The semiconductor device as defined in claim 1 , wherein the first drain or source region and the gate line extending from the first gate electrode are connected through a single common contact.

8. The semiconductor device as defined in claim 3 , wherein the first and the second gate electrodes are formed in a layered structure which comprises a thin metal film and a polysilicon layer, wherein the thin metal film is interposed between the polysilicon layer and the first dielectric film, wherein the first dielectric film is formed on each of the pillar-shaped semiconductor layers, the first and third drain or source regions, and the on substrate dielectric film.

9. The semiconductor device as defined in claim 8 , further comprising a silicide layer formed on a top surface of the polysilicon layer of the integrated combination of the gate electrode and the gate line.