Light emitting structure and method of manufacture thereof
View Patent ↗A semiconductor structure having an electrically conducting silicon substrate and a GaN semiconductor device separated from the substrate by a buffer layer is provided. The buffer layer electrically connects the silicon substrate with the GaN semiconductor device. In addition, a GaN LED arranged in a flip chip orientation on the buffer layer on the substrate is provided.
1. A semiconductor structure comprising:
a package heatsink having a top surface;
a first electrical connection having a top surface and a bottom surface, wherein the bottom surface of the first electrical connection contacts a first portion of the top surface of the package heatsink;
a bottom contact having a top surface and a bottom surface, wherein the bottom surface of the bottom contact contacts the top surface of the first electrical connection;
a silicon diode having a top surface and a bottom surface, wherein the bottom surface of the silicon diode contacts the top surface of the bottom contact;
a top contact having a top surface and a bottom surface, wherein the bottom surface of the top contact contacts the top surface of the silicon diode;
a reflective ohmic p type contact having a top surface and a bottom surface, wherein the bottom surface of the reflective ohmic p type contact contacts the top surface of the top contact;
a multilayer epitaxial structure including, in series: a GaN p type layer adjacent to the top surface of the ohmic p type contact, a multi-quantum well (MQW), a GaN n type layer, and a buffer layer having a top surface;
an electrically conductive silicon substrate layer having a top surface and a bottom surface, wherein the bottom surface of the silicon substrate layer contacts the top surface of the buffer layer;
an ohmic n type contact having a top surface and a bottom surface; and
an aperture penetrating the ohmic n-type contact, penetrating the electrically conductive silicon substrate layer, and reaching a portion of the top surface of the buffer layer.
2. A semiconductor structure as claimed in claim 1 , further comprising:
a first contact wire connecting the ohmic n type contact to the first electrical connection
a second electrical connection having a top surface and a bottom surface, wherein the bottom surface of the second electrical connection contacts a second portion of the top surface of the package heatsink; and
a second contact wire connecting the top contact to the second electrical connection.
3. A semiconductor structure as claimed in claim 2 , wherein the silicon diode is configured to serve as an electrostatic discharge device to protect the multilayer epitaxial structure.
4. A semiconductor structure as claimed in claim 1 , wherein a resistivity of the silicon substrate is less than 1 kΩ.cm and within the range 0.5 to 100 Ω.cm.
5. A semiconductor structure as claimed in claim 4 , wherein the buffer layer is electrically conducting and electrically couples the semiconductor device with the silicon substrate.
6. A semiconductor structure as claimed in claim 5 , wherein the buffer layer comprises at least one AlN layer.
7. A semiconductor structure as claimed in claim 6 , wherein the bottom surface of the silicon substrate layer is a {111} plane.
8. A semiconductor structure as claimed in claim 1 , wherein the bottom surface of the silicon substrate layer comprises at least one groove where at least one side of the groove is a {111} plane.
9. A semiconductor structure as claimed in claim 1 , wherein the silicon diode further comprises p and n type silicon layers.