Universal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters
View Patent ↗A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.
1. A delay cell using dual bias to control a delay of a signal through the delay cell, the delay cell comprising:
coarse current bias control circuitry
fine current bias control circuitry, wherein the coarse current bias control circuitry and fine current bias control circuitry combine to produce a combined mirrored current.
2. The delay cell of claim 1 , wherein in a propagation time through the delay cell is inversely proportional to the mirrored current.
3. The delay cell of claim 1 , where a first current provided by the coarse current bias control circuitry has a greater proportional contribution to the mirrored current than the a first current provided by fine current bias control circuitry.
4. The delay cell of claim 1 , wherein the delay cell is a current starved delay cell.
5. The delay cell of claim 1 , wherein the coarse current bias control circuitry includes a first current mirror and wherein the fine current bias control circuitry includes a second current mirror and wherein the first and second current mirror produce the combined mirrored current.
6. The delay cell of claim 5 , wherein the first current mirror includes a first transistor with its gate connected to its drain and wherein the second current mirror includes a second transistor with its gate connected to its drain, wherein the second transistor has an aspect ratio (W/L) that is greater than the aspect ratio of the first transistor.
7. A delay cell using dual bias to control a delay of a signal through the delay cell, the delay cell comprising:
coarse current bias control circuitry
fine current bias control circuitry, wherein a large delay adjustment can be made by varying the fine current control circuitry without adjusting the coarse current control circuitry.
8. The delay cell of claim 7 , wherein the coarse current bias control circuitry includes a first current mirror and wherein the fine current bias control circuitry includes a second current mirror.
9. The delay cell of claim 8 , wherein the first current mirror includes a first transistor with its gate connected to its drain and wherein the second current mirror includes a second transistor with its gate connected to its drain, wherein the second transistor has an aspect ratio (W/L) that is greater than the aspect ratio of the first transistor.
10. A delay cell using dual bias to control a delay of a signal through the delay cell, the delay cell comprising:
coarse current bias control circuitry
fine current bias control circuitry; wherein the dual bias reduces the current consumption at high switching frequencies.
11. The delay cell of claim 10 , wherein the coarse current bias control circuitry includes a first current mirror and wherein the fine current bias control circuitry includes a second current mirror.
12. The delay cell of claim 11 , wherein the first current mirror includes a first transistor with its gate connected to its drain and wherein the second current mirror includes a second transistor with its gate connected to its drain, wherein the second transistor has an aspect ratio (W/L) that is greater than the aspect ratio of the first transistor.
13. A multi-phase digital pulse width modulator (DPWM) whose power consumption does not linearly increase with switching frequency, allowing significant power savings and improving efficiency of low-power switch-mode power supplies operating at high frequencies, wherein the DPWM has dual biased delay cells, the dual bias delay cells including coarse current bias control circuitry, fine current bias control circuitry; and
wherein the coarse current bias control circuitry and fine current bias control circuitry combine to produce a combined mirrored current.
14. The DPWM of claim 13 , wherein the DPWM is multiphased.
15. The DPWM of claim 13 , wherein the dual biased delay cells are current starved delay cells.
16. The DPWM of claim 13 , wherein the coarse current bias control circuitry includes a first current mirror and wherein the fine current bias control circuitry includes a second current mirror and wherein the first and second current mirror produce the combined mirrored current.
17. The DPWM of claim 16 , wherein the first current mirror includes a first transistor with its gate connected to its drain and wherein the second current mirror includes a second transistor with its gate connected to its drain, wherein the second transistor has an aspect ratio (W/L) that is greater than the aspect ratio of the first transistor.