IP Library Granted Patent US 8,203,378
Granted Patent B2
US 8,203,378 · App. 12/706,992 · Granted Jun 19, 2012

Boosting circuit

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Quick Facts
Patent No.
US 8,203,378
App. No.
12/706,992
Granted
Jun 19, 2012
Kind
B2
Abstract

Provided is a boosting circuit which avoids a malfunction of a peripheral circuit to be connected to the boosting circuit. The boosting circuit includes: a first discharge circuit for discharging a voltage of a first output terminal when a boosting unit stops a boosting operation; and a second discharge circuit for discharging a voltage of a second output terminal. The second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage.

Claims (25)

1. A boosting circuit for boosting and outputting an input power supply voltage, comprising:

a boosting unit for outputting a first boosted voltage and a second boosted voltage higher than the first boosted voltage;

a first output terminal for outputting the first boosted voltage;

a second output terminal for outputting the second boosted voltage;

a first discharge circuit for discharging a voltage of the first output terminal after the boosting unit has stopped a boosting operation; and

a second discharge circuit for discharging a voltage of the second output terminal after the boosting unit has stopped the boosting operation,

wherein the second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage.

2. A boosting circuit for boosting and outputting an input power supply voltage, comprising:

a boosting unit for outputting a first boosted voltage and a second boosted voltage higher than the first boosted voltage;

a first output terminal for outputting the first boosted voltage;

a second output terminal for outputting the second boosted voltage;

a first discharge circuit for discharging a voltage of the first output terminal after the boosting unit has stopped a boosting operation; and

a second discharge circuit for discharging a voltage of the second output terminal after the boosting unit has stopped the boosting operation,

wherein the second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage;

a control terminal for inputting a control signal;

wherein the second discharge circuit comprises:

a first transistor including a source connected to the first output terminal, a drain connected to the second output terminal, and a gate connected to the control terminal;

a second transistor including a source connected to the second output terminal, and a gate connected to the first output terminal; and

a third transistor including a source connected to a predetermined potential, a drain connected to a drain of the second transistor, and a gate connected to the control terminal, and

wherein the predetermined voltage comprises an absolute value of a threshold voltage of the second transistor.

3. The boosting circuit according to claim 2 , wherein the predetermined potential comprises a power supply voltage.

4. The boosting circuit according to claim 2 , wherein the predetermined potential comprises a ground potential.

5. The boosting circuit according to claim 2 , wherein the first transistor comprises a depletion type MOS transistor.

6. The boosting circuit according to claim 5 , wherein the predetermined potential comprises a ground potential.

7. The boosting circuit according to claim 5 , wherein the predetermined potential comprises a power supply voltage.

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2010
From: OTANI, AYAKA; OKA, TOMOHIRO
To: SEIKO INSTRUMENTS INC.
Reel/Frame 023948/0028 →