IP Library Granted Patent US 8,415,765
Granted Patent B2
US 8,415,765 · App. 12/707,209 · Granted Apr 9, 2013

Semiconductor device including a guard ring or an inverted region

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Quick Facts
Patent No.
US 8,415,765
App. No.
12/707,209
Granted
Apr 9, 2013
Kind
B2
Abstract

A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.

Claims (23)

1. A semiconductor device comprising:

a semiconductor substrate having a first conductive type layer;

a first diffusion region which has the first conductive type and is formed in the first conductive type layer;

a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and

a PN junction formed at an interface between the first and the second diffusion regions,

wherein the second diffusion region includes a ring shaped structure,

a lower step portion on a surface of the first conductive type layer is formed such that the PN junction is deeper than a bottom of the ring shaped structure,

the second diffusion region includes a first portion and a second portion, said second portion comprising the ring shaped structure, and

an upper step portion is formed by an upper surface of the first portion and the second portion.

2. The semiconductor device according to claim 1 , wherein the PN junction has a lower breakdown voltage than a breakdown voltage between the first conductive type layer and the second diffusion region.

3. The semiconductor device according to claim 1 , wherein a first conductive type impurity concentration of the first diffusion region is larger than a first conductive type impurity concentration of the first conductive type layer.

4. The semiconductor device according to claim 1 , further comprising:

an insulator layer having an opening which is self-aligned to an edge of the second diffusion region.

5. A semiconductor device comprising:

a semiconductor substrate having a first conductive type layer;

a first diffusion region which has the first conductive type and is formed in the first conductive type layer;

a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region;

a PN junction formed at an interface between the first and the second diffusion regions; and

a guard ring having the second conductive type which surrounds the PN junction,

wherein the second diffusion region has a larger impurity concentration than an impurity concentration of the guard ring,

the guard ring includes a first inverted region which surrounds the first diffusion region, said first inverted region has the second conductive type to which the conductive type of the first diffusion region is inverted, and

said guard ring further includes a second inverted region which surrounds the first inverted region, said second inverted region has the second conductive type to which the conductive type of the first conductive type layer of the semiconductor substrate is inverted.

6. The semiconductor device according to claim 5 , wherein a bottom of the first diffusion region is deeper than a bottom of the second diffusion region, and a bottom of the guard ring is deeper than the bottom of the first diffusion region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2010
From: MASADA, ATSUYA; HORIE, MITSUO
To: PANASONIC CORPORATION
Reel/Frame 024236/0917 →