Semiconductor device

1. A semiconductor device comprising:

an n-type metal oxide semiconductor transistor for electrostatic discharge protection having a multi-finger structure in which a plurality of transistors is integrated, and comprising a plurality of drain regions and a plurality of source regions alternately placed with each other, and a plurality of gate electrodes each placed between each of the plurality of drain regions and each of the plurality of source regions;

wherein the plurality of drain regions is electrically connected to an external connection terminal;

wherein the plurality of source regions is electrically connected to a ground potential supply line through first metal interconnects disposed above and connected to each of the plurality of source regions, and a second metal interconnect connected to each of the first metal interconnects with via-holes having a constant size and placed on each of the first metal interconnects; and

wherein a number of the via-holes placed on the first metal interconnect becomes larger as a distance from the ground potential supply line becomes farther.

2. A semiconductor device according to claim 1 :

wherein the second metal interconnect is introduced along a direction perpendicular to a channel width direction of the n-type metal oxide semiconductor transistor for electrostatic discharge protection;

wherein the first metal interconnects are placed in a direction parallel to the channel width direction of the n-type metal oxide semiconductor transistor for electrostatic discharge protection; and

wherein the second metal interconnect are connected to each of the first metal interconnects via the via-holes disposed above the plurality of source regions.

3. A semiconductor device according to claim 1 , wherein a number ratio of via-holes placed on one of the plurality of source region which is disposed farthest from the ground potential supply line to via-holes placed on another one of the source region which is disposed nearest to the ground potential supply line is less than four.

4. A semiconductor device according to claim 1 , wherein the first metal interconnects and the second metal interconnect include a refractory metal.

5. A semiconductor device according to claim 2 , wherein the via-holes are placed widely in a direction parallel to the channel width direction on the first metal interconnect disposed above and connected to each of the plurality of source regions.

6. A semiconductor device according to claim 2 , wherein the via-holes are placed to concentrate in a portion of each of the first metal interconnects disposed above and connected to each of the plurality of source regions.

7. A semiconductor device according to claim 5 , wherein a number ratio of via-holes placed on one of the plurality of source region which is disposed farthest from the ground potential supply line to via-holes placed on another one of the source region which is disposed nearest to the ground potential supply line is less than four.

8. A semiconductor device comprising:

an n-type metal oxide semiconductor transistor for electrostatic discharge protection having a multi-finger structure in which a plurality of transistors is integrated, and comprising a plurality of drain regions and a plurality of source regions alternately placed with each other, and a plurality of gate electrodes each placed between each of the plurality of drain regions and each of the plurality of source regions;

wherein the plurality of drain regions is electrically connected to an external connection terminal;

wherein the plurality of source regions is electrically connected to a ground potential supply line through each of first metal interconnects disposed above and connected to each of the plurality of source regions, and a second metal interconnect connected to the first metal interconnects with via-holes having a constant size and placed on the first metal interconnects; and

wherein each resistance obtained by adding a line resistance of the second metal interconnect connected the ground potential supply line and a contact resistance by the via-holes are substantially equal one another for each of the plurality of source regions.

9. A semiconductor device according to claim 8 , wherein the via-holes have a constant size, and a number of the via-holes arranged on the first metal interconnects is controlled to substantially equalize the each resistance one another.

10. A semiconductor device according to claim 8 , wherein the via-holes have a constant width, and a length of each of the via-holes arranged on the first metal interconnects is controlled to substantially equalize the each resistance one another.

11. A semiconductor device according to claim 8 , wherein the second metal interconnect has a wider width in a direction parallel to a width of the NMOS transistor for ESD protection as a distance from the ground potential supply line is farther.

12. A semiconductor device comprising:

an n-type metal oxide semiconductor transistor for electrostatic discharge protection having a multi-finger structure in which a plurality of transistors is integrated, and comprising a plurality of drain regions and a plurality of source regions alternately placed with each other, and a plurality of gate electrodes each placed between each of the plurality of drain regions and each of the plurality of source regions;

wherein the plurality of drain regions is electrically connected to an external connection terminal;

wherein the plurality of source regions is electrically connected to a ground potential supply line through each of first metal interconnects disposed above and connected to each of the plurality of source regions, and a second metal interconnect connected to the first metal interconnects with via-holes having a constant width and placed on the first metal interconnects; and

wherein a length of each of the via-holes arranged on the first metal interconnects becomes longer as a distance from the ground potential supply line becomes farther.