Analog-to-digital converter

1. An apparatus, comprising:

a first analog input,

a second analog input,

a comparator, a first input of said comparator being coupled with said first analog input and said second analog input,

a multiplexer, a first input of said multiplexer being coupled with said first analog signal input, a second input of said multiplexer being coupled with said second analog signal input and an output of said multiplexer being coupled with said first input of said comparator,

analog-to-digital conversion circuitry coupled with an output of said comparator and a second input of said comparator,

wherein a first portion of said analog-to-digital conversion circuitry associated with converting a signal applied to said first analog input is implemented at least partially separate from a second portion of said analog-to-digital conversion circuitry associated with converting a signal applied to said second analog input.

2. The apparatus of claim 1 , wherein said first portion comprises a first analog-to-digital conversion algorithm channel, and said second portion comprises a second analog-to-digital conversion algorithm channel separate from said first analog-to-digital conversion algorithm channel.

3. The apparatus of claim 2 , further comprising a demultiplexer, wherein an input of said demultiplexer is coupled with said output of said comparator, a first output of said demultiplexer is coupled with said first analog-to-digital conversion algorithm channel and a second output of said demultiplexer is coupled with said second analog-to-digital conversion algorithm channel .

4. The apparatus of claim 1 , wherein said first and second portion comprise a common analog-to-digital conversion algorithm,

wherein said first portion comprises a first memory portion to store values associated with the conversion of said first signal and said second portion comprises a second memory portion different from said first memory portion to store a value associated with the conversion of said second signal.

5. The apparatus of claim 4 , further comprising a demultiplexer, wherein an input of said demultiplexer is coupled with an output of said analog-to-digital conversion algorithm, wherein a first output of said demultiplexer is coupled with said first memory portion and a second output of said demultiplexer is coupled with said second memory portion.

6. The apparatus of claim 1 , wherein said analog-to-digital conversion circuitry comprises a tracking circuitry.

7. An apparatus, comprising:

a comparator,

a demultiplexer, an input of said demultiplexer being coupled with an output of said comparator,

at least one analog signal input, said at least one analog signal input being coupled with a first input of said comparator, and

a digital-to-analog converter, an output of said digital-to-analog converter being coupled with a second input of said comparator.

8. The apparatus of claim 7 , further comprising a first analog-to-digital conversion algorithm channel coupled to a first output of said demultiplexer, and a second analog-to-digital conversion algorithm channel coupled to a second output of said demultiplexer.

9. The apparatus of claim 8 , wherein said at least one analog signal input comprises a first analog input signal and a second analog input signal, the apparatus further comprising:

a first multiplexer, a first input of said first multiplexer being coupled to said first analog signal input, a second input of said first multiplexer being coupled to said second analog signal input, and an output of said first multiplexer being coupled to said first input of said comparator, and

a second multiplexer, a first input of said second multiplexer being coupled with said first analog-to-digital conversion algorithm channel, a second input of said second multiplexer being coupled to said second analog-to-digital conversion algorithm channel, and an output of said second multiplexer being coupled to an input of said digital-to-analog converter.

10. The apparatus of claim 9 , wherein said first multiplexer, said second multiplexer and said demultiplexer are configured to be switched synchronously.

11. The apparatus of claim 7 , wherein a first output of said demultiplexer is coupled with a comparator output of said apparatus, and wherein a second output of said demultiplexer is coupled with a analog-to-digital conversion algorithm.

12. The apparatus of claim 11 , further comprising offset calculation circuitry coupled to said comparator signal output and to an output of said analog-to-digital conversion algorithm.

13. The apparatus of claim 11 , further comprising a multiplexer and a digital value generator configured to generate a digital value,

wherein an output of said digital value generator is coupled with a first input of said multiplexer,

wherein an output of said analog-to-digital conversion algorithm is coupled with a second input of said multiplexer, and

wherein an output of said multiplexer is coupled with an input of said digital-to-analog converter.

14. The apparatus of claim 13 , wherein said digital value generator is configured to generate said digital value based on an output of said analog-to-digital conversion algorithm.

15. The apparatus of claim 13 , wherein said digital value generator is configured to generate a constant digital value.

16. A method, comprising:

alternately providing analog signals to a comparator,

providing a comparator output to a analog-to-digital conversion circuitry comprising a first portion associated with the conversion of a first one of said analog signals and a second portion associated with the conversion of a second one of said analog signals, wherein said first and second portions are at least partially implemented separately.

17. The method of claim 16 , wherein said alternately providing the comparator output comprising alternately providing the comparator output to a first analog-to-digital conversion algorithm channel of said first portion and a second analog-to-digital conversion algorithm channel of said second portion.

18. The method of claim 16 , wherein said alternately providing the comparator output comprises alternately providing said comparator output to a analog-to-digital conversion algorithm common to said first portion and said second portion, said method further comprising:

alternately providing an output of said analog-to-digital conversion algorithm to a first memory portion of said first portion and a second memory portion of said second portion.

19. The method of claim 16 , further comprising:

providing a analog version of an output of said analog-to-digital conversion algorithm circuitry to said comparator.

20. An apparatus, comprising:

a first analog signal input,

a second analog signal input,

a multiplexer, a first input of said multiplexer being coupled with said first analog signal input and a second input of said multiplexer being coupled with said second analog signal input,

a comparator, a first input of said comparator being coupled with an output of said multiplexer,

a analog-to-digital conversion algorithm, an input of said analog-to-digital conversion algorithm being coupled with an output of said comparator,

a digital-to-analog converter, an input of said digital-to-analog converter being coupled with an output of said analog-to-digital conversion algorithm and an output of said analog-to-digital conversion algorithm being coupled to a second input of said comparator,

a first memory portion coupled with said analog-to-digital conversion algorithm, said first memory portion being configured to store an output value of said analog-to-digital conversion algorithm related to an analog-to-digital conversion of a signal applied to said first signal input, and

a second memory portion different from said first memory portion, said second memory portion being configured to store an output value of said analog-to-digital conversion algorithm related to an analog-to-digital conversion of a signal applied to said second signal input.

21. The apparatus of claim 20 , further comprising a demultiplexer, an input of said demultiplexer being coupled with an output of said analog-to-digital conversion algorithm, a first output of said demultiplexer being coupled with said first memory portion and a second output of said demultiplexer being coupled with said second memory portion, and

a further multiplexer, a first input of said further multiplexer being coupled with said first memory portion, a second input of said further multiplexer being coupled with said second memory portion and an output of said second multiplexer being coupled with a further input of said analog-to-digital conversion algorithm.

22. The apparatus of claim 21 , wherein said multiplexer, said further multiplexer and said demultiplexer are configured to be switched synchronously.