Method of manufacturing semiconductor integrated circuit device
To solve a problem that it becomes difficult to lower contact resistance between nickel-based metal silicide and metal for contact as the result of the miniaturization of the hole. One invention of the present application is a method of manufacturing a semiconductor integrated circuit device having a MISFET subjected to silicidation of a source/drain region and the like by nickel-based metal silicide, the method performing a heat treatment for the upper surface of a silicide film in a non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components, before forming a barrier metal at a contact hole provided at a pre-metal insulating film.
1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:
(a) forming a pre-metal insulating film over a device surface of a semiconductor wafer via an etch stop insulating film;
(b) opening a contact hole passing through the pre-metal insulating film and the etch stop insulating film;
(c) performing a heat treatment for the upper surface of a nickel-based metal silicide film at the bottom of the contact hole in a first non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components;
(d) after the step (c), forming a titanium-based barrier metal film at the upper surface of the pre-metal insulating film and the inner surface of the contact hole;
(e) forming a plug metal layer over the upper surface of the pre-metal insulating film and the titanium-based barrier metal film of the inner surface of the contact hole; and
(f) removing the titanium-based barrier metal film and the plug metal layer outside the contact hole.
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the gas having a nitrogen-hydrogen bond is ammonia gas.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein the first non-plasma reducing vapor phase atmosphere contains hydrogen gas as one of main components.
4. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein the first non-plasma reducing vapor phase atmosphere contains hydrogen gas as the most plentiful component.
5. The method of manufacturing a semiconductor integrated circuit device according to claim 4 , wherein the first non-plasma reducing vapor phase atmosphere contains an inert gas as one of main components.
6. The method of manufacturing a semiconductor integrated circuit device according to claim 4 , wherein the first non-plasma reducing vapor phase atmosphere contains argon gas as one of main components.
7. The method of manufacturing a semiconductor integrated circuit device according to claim 6 , wherein the first non-plasma reducing vapor phase atmosphere does not substantially contain any of oxygen gas, halogen gas, and organic gas.
8. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein the plug metal layer includes a tungsten-based metal layer as a main constituent.
9. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the gas having a nitrogen-hydrogen bond is ammonia gas is hydrazine gas.
10. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the step (d) includes the substeps of:
(d1) after the step (c), forming a titanium-based metal film at the upper surface of the pre-metal insulating film and the inner surface of the contact hole, and
(d2) forming a titanium nitride film at the upper surface of the titanium-based metal film by performing a plasma nitridation treatment at the upper surface of the titanium-based metal film.
11. The method of manufacturing a semiconductor integrated circuit device according to claim 10 , wherein the step (c) and the substep (d1) are performed over a first wafer stage in a first CVD treatment chamber.
12. The method of manufacturing a semiconductor integrated circuit device according to claim 11 , wherein the step (c) and the substep (d2) are performed over the first wafer stage in the first CVD treatment chamber.
13. The method of manufacturing a semiconductor integrated circuit device according to claim 12 , wherein the step (d) further includes the substep of
(d3) after the substep (d1) and before the substep (d2), performing a heat treatment for the upper surface of the nickel-based metal silicide film via the titanium-based metal film in a second non-plasma reducing vapor phase atmosphere containing a gas having a nitrogen-hydrogen bond as one of main gas components.
14. The method of manufacturing a semiconductor integrated circuit device according to claim 13 , wherein the step (c) and the substep (d3) are performed over the first wafer stage in the first CVD treatment chamber.
15. The method of manufacturing a semiconductor integrated circuit device according to claim 14 , wherein the step (d) further includes the substep of
(d4) after the substep (d1) and before the substep (d3), performing a vapor phase plasma treatment with hydrogen gas as a main component for the device surface side of the semiconductor wafer.
16. The method of manufacturing a semiconductor integrated circuit device according to claim 15 , wherein the step (c) and the substep (d4) are performed over the first wafer stage in the first CVD treatment chamber.
17. The method of manufacturing a semiconductor integrated circuit device according to claim 10 , wherein the substep (d1) is performed by a plasma CVD method.
18. The method of manufacturing a semiconductor integrated circuit device according to claim 17 , wherein the step (d) further includes the substep of
(d5) after the step (c) and before the substep (d1), performing a treatment approximately the same as that in the substep (d1) in a state of applying no plasma.
19. The method of manufacturing a semiconductor integrated circuit device according to claim 18 , wherein the step (c) and the substep (d5) are performed over the first wafer stage in the first CVD treatment chamber.
20. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein a contact structure formed in the contact hole is a shared contact.