Semiconductor device and a method of manufacturing the same and designing the same
View Patent ↗There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP 1 of relatively wider area and the second dummy pattern DP 2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP 1 occupy a relatively wide region among the dummy region FA.
1. A semiconductor device comprising:
semiconductor elements formed in a semiconductor substrate;
a first interlayer insulation film formed over the semiconductor elements;
a first wiring, a plurality of first dummy wirings and a plurality of second dummy wirings formed over the first interlayer insulation film, respectively; and
a second interlayer insulation film formed over the first wiring, the first dummy wirings and the second dummy wirings,
wherein the first wiring is electrically connected with the semiconductor elements,
wherein the first dummy wirings and the second dummy wirings are not electrically connected with the semiconductor elements,
wherein a planar size of each of the first dummy wirings is larger than a planar size of each of the second dummy wirings,
wherein each of the first dummy wirings is arranged with same pitch,
wherein each of the second dummy wirings is arranged with same pitch, and
wherein the second dummy wirings are arranged next to the first wiring, and between the first wiring and the first dummy wirings.
2. The semiconductor device according to claim 1 ,
wherein the first wiring, the first dummy wirings and the second dummy wirings are formed of a copper as a major component.
3. The semiconductor device according to claim 1 ,
wherein the second interlayer insulation film is polished by CMP method.
4. The semiconductor device according to claim 3 ,
wherein the surface of the second interlayer insulation film is flat.
5. The semiconductor device according to claim 1 , further comprising:
a plurality of third dummy wirings formed over the second interlayer insulation film,
wherein the third dummy wirings are not electrically connected with the semiconductor elements, and
wherein each of the third dummy wirings is arranged with same pitch.
6. The semiconductor device according to claim 5 ,
wherein the third dummy wirings are formed of a copper as a major component.
7. The semiconductor device according to claim 1 ,
wherein the semiconductor elements are MOSFETs, respectively.
8. The semiconductor device according to claim 1 ,
wherein the pitch of the first dummy wirings is larger than the pitch of the second dummy wirings.