Solid state disk device and related data storing and reading methods
A solid state disk device comprises a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are electrically connected to a plurality of channels, respectively. The controller controls storing, erasing and reading operations of the nonvolatile memories. The controller divides input data into a number of units corresponding to a number of the plurality of channels and stores the divided input data in the nonvolatile memories through the plurality of channels.
1. Device storage device using nonvolatile memories, comprising:
N nonvolatile memories electrically connected to N channels, respectively, where N is a number greater than one; and
a controller that controls storing, erasing and reading operations of the N nonvolatile memories,
wherein the controller receives a unit of input data and divides the unit of input data into N data sub-units and stores the N data sub-units in the N nonvolatile memories, respectively, via the corresponding N channels, and
wherein the controller comprises:
an error correction engine that generates parity information corresponding to the unit of input data; and
a direct memory access (DMA) control unit that divides the unit of input data into the N sub-units, divides the parity information into N parity sub-units, and transmits the N parity sub-units to the N nonvolatile memories, respectively, via the N channels.
2. The storage device of claim 1 , wherein the error correction engine is shared by the N channels.
3. The storage device of claim 1 , wherein the error correction engine generates the parity information before the DMA divides the unit of input data into the N data sub-units.
4. The storage device of claim 1 , wherein the DMA control unit comprises a data division unit that divides the unit of input data and the parity information into the N data sub-units and N parity sub-units.
5. The storage device of claim 1 , wherein the controller further comprises a central processing unit (CPU) connected to the DMA controller via a CPU bus.
6. The storage device of claim 5 , wherein the DMA control unit simultaneously transmits the N data sub-units and N parity sub-units to the N nonvolatile memories via the N channels such that the data sub-units and parity sub-units do not pass through the CPU bus.
7. The storage device of claim 1 , wherein the unit of input data is a unit for generating the parity information of error correction engine.
8. The storage device of claim 1 , wherein a data size of the unit of input data is the same as a data size of a page of each nonvolatile memory.
9. The storage device of claim 1 , wherein the DMA control unit comprises a demultiplexer that performs data division operations.
10. The storage device of claim 1 , wherein the controller further comprises a flash translation layer that maintains a mapping between physical addresses of the input data stored in the nonvolatile memories and logical addresses of the input data from a host.
11. The storage device of claim 10 , wherein the controller further comprises a host interface configured to connect the host to the controller, and the host interface is one of PCI, SATA and SCSI interfaces.
12. A method of storing data in a solid state disk device, comprising:
receiving a store command and a unit of input data from a host;
generating parity information using an error correction engine, the parity information corresponding to the unit of input data;
dividing the input data into N data sub-units and the parity information into N parity sub-units, wherein N is a number greater than one;
transmitting via N respective channels the N data sub-units and the N parity sub-units to a respective plurality of nonvolatile memories in the solid state disk device; and
storing the N data sub-units and N parity sub-units transmitted via the N respective channels in the respective plurality of nonvolatile memories.
13. The data storing method of claim 12 , wherein the parity information is generated by an error correction engine shared by at least two of the channels.
14. The data storing method of claim 12 , wherein the transmitting the N data sub-units and N parity sub-units to the respective plurality of nonvolatile memories via the N respective channels does not pass through a bus of a central processing unit (CPU).
15. The data storing method of claim 12 , wherein dividing the input data and the parity information comprises performing a demultiplexing operation.
16. A method of reading data in a solid state disk device, comprising:
receiving a read command from a host;
in response to the read command, reading a plurality of data sub-units and a plurality of corresponding parity sub-units stored in a respective plurality of nonvolatile memory devices in the solid state disk device via a respective plurality of channels, wherein the number of the plurality data sub-units and the number of the plurality of parity sub-units equals the number of channels;
generating parity information from the plurality of data sub-units;
comparing the generated parity information with the plurality of parity sub-units to determine whether the data sub-units contain any errors;
correcting any errors detected in the data sub-units through the comparison and outputting the resulting corrected data.
17. The data reading method of claim 16 , wherein the generating, comparing, and correcting are performed by an error correction engine shared by two or more channels.
18. The data reading method of claim 16 , wherein the nonvolatile memory devices comprise multi-bit flash memory devices.
19. The data reading method of claim 16 , further comprising assembling the plurality of data sub-units into a page of data prior to outputting the corrected data.
20. The data reading method of claim 16 , further comprising:
prior to outputting the corrected data, mapping logical addresses of the corrected data to physical addresses of the corrected data.