Reduced current input buffer circuit

1. A method, comprising:

providing an input buffer with only a portion of a normal operating current of the input buffer;

determining whether data is expected to be received at the input buffer; and

if data is expected to be received at the input buffer, providing the input buffer with the normal operating current by activating at least one enabling transistor utilizing a bias signal,

wherein the bias signal is produced using an inverse of an enable signal NORed with a CLOCK signal.

2. The method, as set forth in claim 1 , wherein determining is dependent on a state of one or more control signals of the input buffer.

3. The method, as set forth in claim 2 , wherein determining comprises determining whether a CLOCK signal is in a low state.

4. The method, as set forth in claim 1 , wherein the method begins when a system having the input buffer therein is powered up.

5. The method, as set forth in claim 1 , wherein the method begins when the input buffer is enabled after a period of non-use.

6. The method, as set forth in claim 1 , comprising:

operating the input buffer at a normal operating current while data is received; and

providing only a portion of the normal operating current to the input buffer after the data is received.

7. A method, comprising:

providing a first portion of a full operating current to an input buffer, utilizing first buffer enabling circuitry; and

providing a second portion of the full operating current to the input buffer, utilizing second buffer enabling circuitry comprising at least one enabling transistor that is activated by a bias signal, the bias signal being produced using an inverse of an enable signal NORed with a CLOCK signal,

wherein the second buffer enabling circuitry is different than the first buffer enabling circuitry,

wherein the first and second portions of the full operating current comprise a normal operating current of the input buffer.

8. The method, as set forth in claim 7 , wherein providing the first portion comprises providing sufficient current to maintain proper operating levels of internal circuitry of the input buffer.

9. The method, as set forth in claim 7 , wherein providing the second portion occurs only when the input buffer is expecting to receive data.

10. The method; as set forth in claim 7 , comprising withholding the second portion of the full operating current from the input buffer when the input buffer is not expecting to receive data.

11. The method, as set forth in claim 10 , wherein withholding the second portion of the operating current from the input buffer is responsive to a transition of the CLOCK signal.

12. The method, as set forth in claim 7 , wherein the first buffer enabling circuitry comprises at first plurality of transistors.

13. A method, comprising:

providing a first portion of a normal operating current to an input buffer; and

providing a second portion of the normal operating current to the input buffer if the input buffer is expecting data,

wherein providing the second portion of the operating current comprises activating at least one enabling transistor utilizing a bias signal,

wherein the bias signal is produced using an inverse of an enable signal NORed with a CLOCK signal.

14. The method, as set forth in claim 13 , comprising withholding the second portion of tile normal operating current from the input buffer responsive to the CLOCK signal.

15. The method, as set forth in claim 13 , wherein providing the first portion comprises providing sufficient current to maintain proper operating levels of internal circuitry of the input buffer.

16. The method, as set forth in claim 13 , wherein providing the first portion of the normal operating current comprises providing less than 30% of the normal operating current to the input buffer.

17. The method, as set forth in claim 13 , wherein providing the first portion of the normal operating current comprises providing less than 10% of the normal operating current to the input buffer.