Thin film transistor array panel with common bars of different widths
View Patent ↗A gate wire and a storage electrode wire extending in a transverse direction are provided, and a data wire extending in a longitudinal direction intersects the gate wire and the storage electrode wire. A plurality of pixel electrodes and a plurality of TFTs are provided on pixel areas defined by the intersections of the data wire and the gate wire. The storage electrode wire is interconnected by a plurality of storage electrodes connections provided on the pixel areas. In this way, a common bar disposed between gate pads and a display area is omitted or has reduced width. Therefore, the fan-out areas becomes to have sufficient size to reduce the resistance difference between the signal lines.
1. A thin film transistor array panel comprising:
an insulating substrate;
an active area displaying images, and comprising a pixel electrode electrically connected to a thin film transistor;
a peripheral area surrounding the active area, and comprising a first portion and a second portion being opposite to the first portion with the active area therebetween;
a storage electrode line insulated from the thin film transistor, and at least partially overlapping the pixel electrode;
a first common bar having a first width, disposed on the first portion, and electrically connected to one side of the storage electrode line; and
a second common bar having a second width different from the first width, disposed on the second portion, and electrically connected to another side of the storage electrode line.
2. The thin film transistor array panel of claim 1 , further comprising:
a gate line electrically connected to the thin film transistor, and
a first pad disposed on the first porion, and electrically connected to the gate line,
wherein the first common bar is disposed between the gate pad and the pixel area, and the first width is smaller than the second width.
3. The thin film transistor array panel of claim 2 , further comprising a fan-out portion between the first pad and the first common bar.
4. The thin film transistor array panel of claim 3 , further comprising a storage pad electrically connected to the second common bar.
5. The thin film transistor array panel of claim 4 , wherein the first common bar is disposed on a different layer than the storage electrode line.
6. The thin film transistor array panel of claim 1 , further comprising a storage pad electrically connected to the second common bar.
7. The thin film transistor array panel of claim 6 , further comprising:
a gate line electrically connected to the thin film transistor, and
a first pad disposed on the first porion, and electrically connected to the gate line,
wherein the first common bar is disposed between the gate pad and the pixel area, and the first width is smaller than the second width.
8. The thin film transistor array panel of claim 7 , wherein the first common bar is disposed on a different layer than the storage electrode line.
9. The thin film transistor array panel of claim 6 wherein the first common bar is disposed on a different layer than the storage electrode line.
10. The thin film transistor array panel of claim 1 , wherein the first common bar is disposed on a different layer than the storage electrode line.
11. The thin film transistor array panel of claim 10 , further comprising:
a gate line electrically connected to the thin film transistor, and
a first pad disposed on the first porion, and electrically connected to the gate line,
wherein the first common bar is disposed between the gate pad and the pixel area, and the first width is smaller than the second width.
12. The thin film transistor array panel of claim 11 , further comprising a fan-out portion between the first pad and the first common bar.