Semiconductor device having a junction FET and a MISFET for control
View Patent ↗A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
1. A semiconductor device comprising a junction FET as a main transistor and a MISFET as a transistor for control, wherein
the junction FET has a first gate electrode, a first source electrode, and a first drain electrode,
the MISFET has a second gate electrode, a second source electrode, and a second drain electrode,
the MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET,
the second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting, and
the first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
2. The semiconductor device according to claim 1 , wherein
the junction FET and the MISFET are disposed on a same semiconductor substrate,
on the semiconductor substrate, the junction FET has:
(a1) an n-type drift layer;
(a2) a first n-type source layer formed in the n-type drift layer; and
(a3) a p-type gate layer formed in the n-type drift layer and electrically connected to the first n-type source layer,
on the semiconductor substrate, the MISFET has:
(b1) a p-type well layer formed in the n-type drift layer;
(b2) a gate electrode formed on the p-type well layer interposing a gate insulating film; and
(b3) a second n-type source layer and a second n-type drain layer formed in the p-type well layer at side lower portions of the gate electrode,
the p-type gate layer and the second n-type source layer are formed to have a junction part,
the p-type gate layer and the p-type well layer are formed to have a junction part,
the first source electrode is formed to be electrically connected to the first n-type source layer,
the first drain electrode is formed to be electrically connected to the semiconductor substrate,
the first gate electrode and the second source electrode are formed to be mutually integrated and be electrically connected to the p-type gate layer and the second n-type source layer, and
the second gate electrode and the second drain electrode are formed to be mutually integrated and be electrically connected to the gate electrode and the second n-type drain layer.
3. The semiconductor device according to claim 2 , wherein
the semiconductor substrate is a semiconductor material mainly composed of SiC.
4. The semiconductor device according to claim 1 , wherein
the junction FET is disposed on a first semiconductor substrate;
the MISFET is disposed on a second semiconductor substrate; and
the first semiconductor substrate and the second semiconductor substrate are sealed in a same package.
5. The semiconductor device according to claim 4 , wherein,
on the first semiconductor substrate, the junction FET has:
(a1) an n-type drift layer;
(a2) a first n-type source layer formed in the n-type drift layer; and
(a3) a p-type gate layer formed in the n-type drift layer and electrically connected to the first n-type source layer; and,
on the second semiconductor substrate, the MISFET has:
(b1) a p-type well layer;
(b2) a gate electrode formed on the p-type well layer interposing a gate insulating film; and
(b3) a second n-type source layer and a second n-type drain layer formed in the p-type well layer at side lower portions of the gate electrode.
6. The semiconductor device according to claim 5 , wherein
the first semiconductor substrate is formed of a semiconductor material mainly composed of SiC.
7. The semiconductor device according to claim 6 , wherein
the first semiconductor substrate and the second semiconductor substrate are disposed on a same base plate,
a source terminal electrode, a drain terminal electrode, and a gate terminal electrode capable of being electrically connected to outside of the package are disposed on the base plate,
an intermediate terminal electrode is disposed on the base plate,
the first source electrode is formed on an upper surface of the first semiconductor substrate to be electrically connected to the first n-type source layer,
the first gate electrode is formed on the upper surface of the first semiconductor substrate to be electrically connected to the p-type gate layer,
the first drain electrode is formed on a lower surface of the first semiconductor substrate to be electrically connected to the first semiconductor substrate,
the second source electrode is formed at two locations, that is, on an upper surface and a lower surface of the second semiconductor substrate to be electrically connected to the second n-type source layer,
the second gate electrode is formed on the upper surface of the second semiconductor substrate to be electrically connected to the gate electrode,
the second drain electrode is formed on the upper surface of the second semiconductor substrate to be electrically connected to the second n-type drain layer,
the first drain electrode on the lower surface of the first semiconductor substrate and the drain terminal electrode are electrically bonded with each other by soldering,
the second source electrode on the lower surface of the second semiconductor substrate and the intermediate terminal electrode are electrically bonded with each other by the soldering,
the first source electrode and the source terminal electrode are electrically connected to each other by a metal wire,
the first gate electrode is electrically connected to the second source electrode and the intermediate terminal electrode by the metal wire, and
the second gate electrode and the second drain electrode are electrically connected to the gate terminal electrode by the metal wire.
8. The semiconductor device according to claim 6 , wherein
the first semiconductor substrate and the second semiconductor substrate are disposed on a same base plate,
a source terminal electrode, a drain terminal electrode, and a gate terminal electrode capable of being electrically connected to outside of the package are disposed on the base plate,
an intermediate terminal electrode is disposed on the base plate,
the first source electrode is formed on an upper surface of the first semiconductor substrate to be electrically connected to the first n-type source layer,
the first gate electrode is formed on the upper surface of the first semiconductor substrate to be electrically connected to the p-type gate layer,
the first drain electrode is formed on a lower surface of the first semiconductor substrate to be electrically connected to the first semiconductor substrate,
the second source electrode is formed on a lower surface of the second semiconductor substrate to be electrically connected to the second n-type source layer,
the second gate electrode is formed on the upper surface of the second semiconductor substrate to be electrically connected to the gate electrode,
the second drain electrode is formed on the upper surface of the second semiconductor substrate to be electrically connected to the second n-type drain layer,
the first drain electrode on the lower surface of the first semiconductor substrate and the drain terminal electrode are electrically bonded with each other by soldering,
the second source electrode on the lower surface of the second semiconductor substrate and the intermediate terminal electrode are electrically bonded with each other by the soldering,
the first source electrode and the source terminal electrode are electrically connected to each other by a metal wire,
the first gate electrode and the intermediate terminal electrode are electrically connected by the metal wire, and
the second gate electrode and the second drain electrode are electrically connected to the gate terminal electrode by the metal wire.
9. The semiconductor device according to claim 6 , wherein
the first semiconductor substrate and the second semiconductor substrate are disposed on a same base plate,
a source terminal electrode, a drain terminal electrode, and a gate terminal electrode capable of being electrically connected to outside of the package are disposed on the base plate,
the first source electrode is formed on an upper surface of the first semiconductor substrate to be electrically connected to the first n-type source layer,
the first gate electrode is formed on the upper surface of the first semiconductor substrate to be electrically connected to the p-type gate layer,
the first drain electrode is formed on a lower surface of the first semiconductor substrate to be electrically connected to the first semiconductor substrate,
the second source electrode is formed on an upper surface of the second semiconductor substrate to be electrically connected to the second n-type source layer,
the second gate electrode is formed on the upper surface of the second semiconductor substrate to be electrically connected to the gate electrode,
the second drain electrode is formed on the lower surface of the second semiconductor substrate to be electrically connected to the second n-type drain layer,
the first drain electrode on the lower surface of the first semiconductor substrate and the drain terminal electrode are electrically bonded with each other by soldering,
the second drain electrode on the lower surface of the second semiconductor substrate and the gate terminal electrode are electrically bonded with each other by the soldering,
the first source electrode and the source terminal electrode are electrically connected to each other by a metal wire,
the first gate electrode and the second source electrode are electrically connected by the metal wire, and
the second gate electrode and the gate terminal electrode are electrically connected by the metal wire.
10. The semiconductor device according to claim 1 , wherein
the junction FET and the MISFET are composed of mutually different packages and are disposed on a same printed circuit board.
11. A semiconductor device comprising a boost chopper, wherein
the boost chopper has a switching element,
the switching element is composed of a junction FET serving as a main transistor and a MISFET serving as a transistor for control,
the junction FET has a first gate electrode, a first source electrode, and a first drain electrode,
the MISFET has a second gate electrode, a second source electrode, and a second drain electrode,
the MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET,
the second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting, and
the first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
12. A semiconductor device comprising an inverter, wherein
the inverter has a plurality of switching elements,
each of the switching elements are composed of a junction FET serving as a main transistor and a MISFET serving as a transistor for control,
the junction FET has a first gate electrode, a first source electrode, and a first drain electrode,
the MISFET has a second gate electrode, a second source electrode, and a second drain electrode,
the MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET,
the second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting, and
the first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
13. The semiconductor device according to claim 12 , wherein
the plurality of switching elements further has a first diode, and
the first diode is connected to the junction FET in parallel.