ESD PROTECTION VERIFICATION APPARATUS AND METHOD
An ESD protection verification apparatus of an aspect of the present invention including an element extraction unit which extracts one or more elements connected to a first pad included in design data for a semiconductor integrated circuit, a first and second element information checking/processing unit which checks connection information for the extracted element and which calculates a operating value based on design information for the extracted element, a first and second error detection unit which compares a reference value with the operating value to determine whether the element has a predetermined ESD withstand voltage.
1 . An ESD protection verification apparatus comprising:
an element extraction unit which extracts one or more elements connected to a first pad included in design data for a semiconductor integrated circuit;
a first element information checking/processing unit which checks connection information for the extracted element to determine one or more first connection information elements and which calculates a first operating value based on design information for the first connection information element, the first connection information element being configured so that a first electrode of the extracted element is connected to the first pad;
a first error detection unit which compares a first reference value with the first operating value to determine whether the first connection information element has a predetermined ESD withstand voltage;
a second element information checking/processing unit which checks connection information for the first connection information element to determine one or more second connection information elements and which calculates a second operating value based on design information for the second connection information element, the second connection information element being configured so that a second electrode of the first connection information element is connected to a second pad different from the first pad; and
a second error detection unit which compares a second reference value with the second operating value to determine whether the second connection information element has a predetermined ESD withstand voltage.
2 . The ESD protection verification apparatus according to claim 1 , further comprising:
an element group detection unit which checks the extracted element to find out whether the second electrode is connected to a pad other than the first pad, and detects an element connected to the second electrode when the second electrode is connected to no pad.
3 . The ESD protection verification apparatus according to claim 1 , further comprising:
an error correction unit which corrects the design information for the first or second connection information element not having the predetermined ESD withstand voltage when the first or second connection information element is determined not to have the predetermined ESD withstand voltage.
4 . The ESD protection verification apparatus according to claim 1 , further comprising:
a storage device which stores the design information and ESD withstand voltage information corresponding to the design information, wherein the design information indicates dimensions corresponding to a plurality of elements in the design data.
5 . The ESD protection verification apparatus according to claim 1 , wherein
the element extraction unit extracts a diode constituting a circuit, an ESD protection diode and a parasitic diode.
6 . The ESD protection verification apparatus according to claim 5 , wherein
the first operating value is a value based on at least one of the area, circumference, length and width of each of the diode, the ESD protection diode and the parasitic diode.
7 . The ESD protection verification apparatus according to claim 1 , wherein
when two or more first connection information elements are determined, the first element information checking/processing unit calculates the sum of the dimensions of the first connection information elements as the first operating value.
8 . The ESD protection verification apparatus according to claim 1 , wherein
when two or more second connection information elements are determined, the second element information checking/processing unit calculates the sum of the dimensions of the second connection information elements as the second operating value by using, as one unit, two or more second connection information elements connected to the same second pad.
9 . An ESD protection verification apparatus comprising:
an element extraction unit which selects one first pad from a plurality of pads included in design data for a semiconductor integrated circuit and extracts an element connected to the selected first pad;
an element information examining unit which checks design information for the extracted element;
a processing unit which calculates an operating value indicating operating characteristics of the extracted element on the basis of the checked design information; and
an error detection unit which compares the operating value with a reference value and determines whether the extracted element has a predetermined ESD withstand voltage.
10 . The ESD protection verification apparatus according to claim 9 , further comprising:
an error correction unit which corrects the dimension of the element not having the predetermined ESD withstand voltage in the design data when the extracted element is determined not to have the predetermined ESD withstand voltage.
11 . The ESD protection verification apparatus according to claim 9 , further comprising:
a storage device which stores information on operating characteristics corresponding to a plurality of elements in the design data, and ESD withstand voltage information corresponding to the operating characteristics information.
12 . The ESD protection verification apparatus according to claim 9 , wherein
the extracted element is directly connected to the first pad.
13 . The ESD protection verification apparatus according to claim 9 , wherein
the element extraction unit extracts a field effect transistor and a parasitic transistor.
14 . The ESD protection verification apparatus according to claim 9 , wherein
the operating characteristics are a snapback voltage of a transistor.
15 . An ESD protection verification method comprising:
extracting one or more elements connected to a first pad included in design data for a semiconductor integrated circuit;
checking connection information for the extracted element to determine one or more first connection information elements, and calculating a first operating value based on design information for the first connection information element, the first connection information element being configured so that a first electrode of the extracted element is connected to the first pad;
comparing a first reference value with the first operating value to determine whether the first connection information element has a predetermined ESD withstand voltage;
checking connection information for the first connection information element to determine one or more second connection information elements, and calculating a second operating value based on design information for the second connection information element, the second connection information element being configured so that a second electrode of the first connection information element is connected to a second pad different from the first pad; and
comparing a second reference value with the second operating value to determine whether the second connection information element has a predetermined ESD withstand voltage.
16 . The ESD protection verification method according to claim 15 , further comprising:
correcting the design data for the first or second connection information element not having the predetermined ESD withstand voltage when the first or second connection information element does not have the predetermined ESD withstand voltage.
17 . The ESD protection verification method according to claim 15 , further comprising:
determining whether the second electrode of the first connection information element is connected to a pad exclusive of the first pad or to an electrode of another element.
18 . The ESD protection verification method according to claim 15 , wherein
the extracted element is an ESD protection diode, a diode constituting a circuit, and a parasitic diode.
19 . The ESD protection verification method according to claim 15 , wherein
the extracted element is a field effect transistor and a parasitic transistor in which one end of a current path is directly connected to the first pad.
20 . The ESD protection verification method according to claim 15 , wherein
the design information indicates at least one of a dimension of the element and electrical properties of the element.