Methods and apparatus for reducing defect bits in phase change memory
View Patent ↗Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
1. A method for operating a memory cell comprising memory material and programmable to a plurality of resistance states including a higher resistance state and a lower resistance state, the method comprising:
applying a first bias arrangement to the memory cell to establish the higher resistance state;
after applying the first biasing arrangement, applying a first voltage to the memory cell to induce a first current in the memory cell;
after applying the first biasing arrangement, applying a second voltage to the memory cell to induce a second current in the memory cell, the second voltage different from the first voltage; and
if the first and second currents differ by a threshold, then applying a second bias arrangement to the memory cell to establish the higher resistance state.
2. The method of claim 1 , wherein the memory material comprises phase change material.
3. The method of claim 1 , including determining if the first and second currents differ by a threshold by determining whether a ratio of a difference between the first and second currents to a difference between the first and second voltages is above a particular ratio.
4. The method of claim 2 , wherein a condition in which the first and second currents differ by the threshold indicates an amount of amorphous phase change material within an active region of the phase change material of the memory cell.
5. The method of claim 1 , further comprising after said applying the second bias arrangement, the steps of:
applying a third voltage to the memory cell to induce a third current in the memory cell;
applying a fourth voltage to the memory cell to induce a fourth current in the memory cell; and
if the third and fourth currents differ by said threshold or by a different threshold, then applying a third bias arrangement to the memory cell to establish the higher resistance state based on the first and second currents.
6. The method of claim 5 , further comprising iterating the steps of applying the third and fourth voltages and the third bias arrangement, until a difference between the third and fourth currents is below said threshold or said different threshold, or a particular number of retries are made.
7. The method of claim 6 , further comprising replacing the memory cell with a replacement cell if the particular number of retries are made.
8. The method of claim 1 , wherein:
the first bias arrangement induces a first reset current in the memory cell; and
the second bias arrangement induces a second reset current in the memory cell, the second reset current having a magnitude greater than that of the first reset current.
9. A memory device comprising:
a memory cell comprising memory material and programmable to a plurality of resistance states including a higher resistance state and a lower resistance state;
bias circuitry to apply a first bias arrangement to the memory cell to establish the higher resistance state, after applying the first biasing arrangement, to apply a first voltage to the memory cell to induce a first current in the memory cell, after applying the first biasing arrangement, to apply a second voltage to the memory cell different from the first voltage to induce a second current in the memory cell, and if the first and second currents differ by a threshold, then to apply a second bias arrangement to the memory cell to establish the higher resistance state; and
sense circuitry to sense the first and second currents.
10. The memory device of claim 9 , wherein the memory material comprises phase change material.
11. The memory device of claim 9 , wherein said selectively applying the second bias arrangement is in response to a command signal.
12. The memory device of claim 11 , further comprising control circuitry which generates the command signal based on the sensed first and second currents.
13. The memory device of claim 12 , wherein the control circuitry generates the command signal if a difference between the first and second currents is above a threshold.
14. The memory device of claim 12 , wherein the control circuitry generates the command signal if a ratio of a difference between the first and second currents to a difference between the first and second voltages is above a particular ratio.
15. The memory device of claim 13 , wherein:
the memory material comprises phase change material; and
said difference indicates an amount of amorphous phase change material within an active region of the phase change material of the memory cell.
16. The memory device of claim 9 , wherein:
said bias circuitry further to apply after applying the second bias arrangement, a third voltage to the memory cell to induce a third current in the memory cell, to apply a fourth voltage to the memory cell to induce a fourth current in the memory cell, and apply a third bias arrangement to the memory cell to establish the higher resistance state in response to a second command signal, and if the third and fourth currents differ by said threshold or a different threshold, then to apply a third bias arrangement to the memory cell to establish the higher resistance state.
17. The memory device of claim 16 , wherein said bias circuitry iteratively applies the third and fourth voltages and the third bias arrangement, until said third and fourth currents differ by said threshold or said different threshold or a particular number of retries are made.
18. The memory device of claim 17 , further comprising:
an array of memory cells including said memory cell; and
a set of replacement cells to provide replacements for memory cells in the array, and wherein the control circuitry includes resources for replacing said memory cell with a replacement cell in the set of replacement cells if the particular number of retries are made.
19. The memory device of claim 9 , wherein:
the first bias arrangement induces a first reset current in the memory cell; and
the second bias arrangement induces a second reset current in the memory cell, the second reset current having a magnitude greater than that of the first reset current.
20. The memory device of claim 16 , wherein:
said sense circuitry further senses the third and fourth currents, and generates a second command signal if a difference between the third and fourth currents is above said threshold or said different threshold.