Latch circuit

1. A latch circuit comprising:

an input part receiving an external input signal;

a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the external input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the external input signal; and

a feedback path through which the external input signal is fed back to the input part via the plurality of CMOS inverter circuits,

wherein

a first pMOS region, a first nMOS region, a second pMOS region, and a second nMOS region are arranged in the semiconductor substrate in order,

the first CMOS inverter circuit includes a first P-polarity drain formed in the first pMOS region and a first N-polarity drain formed in the second nMOS region, and

the second CMOS inverter circuit includes a second P-polarity drain formed in the second pMOS region and a second N-plurality drain formed in the first nMOS region.

2. The latch circuit according to claim 1 ,

wherein

the third CMOS inverter circuit includes a third P-polarity drain formed in the second pMOS region and a third N-polarity drain formed in the first nMOS region, and

the fourth CMOS inverter circuit includes a fourth P-polarity drain formed in the first pMOS region and a fourth N-polarity drain formed in the second nMOS region.

3. The latch circuit according to claim 2 , wherein

the first P-polarity drain is adjacent to the second N-polarity drain, and

the second P-polarity drain is adjacent to the first N-polarity drain, and

the third P-polarity drain is adjacent to the fourth N-polarity drain, and

the fourth P-polarity drain is adjacent to the third N-polarity drain.

4. The latch circuit according to claim 1 ,

wherein the first CMOS inverter circuit and the second CMOS inverter circuit use a common gate over the first pMOS region and the first nMOS region.

5. The latch circuit according to claim 1 ,

wherein the first CMOS inverter circuit and the second CMOS inverter circuit use a common gate over the second pMOS region and the second nMOS region.

6. The latch circuit according to claim 1 ,

wherein the output from the first CMOS inverter circuit is coupled to the gate of a second-polarity transistor in the third CMOS inverter circuit and the gate of a first-polarity transistor in the fourth CMOS inverter circuit,

wherein the output from the second CMOS inverter circuit is coupled to the gate of a first-polarity transistor in the third CMOS inverter circuit and the gate of a second-polarity transistor in the fourth CMOS inverter circuit,

wherein the output from the third CMOS inverter circuit is coupled to the gate of a first-polarity transistor in the first CMOS inverter circuit and the gate of a second-polarity transistor in the second CMOS inverter circuit, and

wherein the output from the fourth CMOS inverter circuit is coupled to the gate of a second-polarity transistor in the first CMOS inverter circuit and the gate of a first-polarity transistor in the second CMOS inverter circuit.

7. The latch circuit according to claim 6 ,

wherein the input part includes the gates of the first-polarity transistor in the first CMOS inverter circuit and the second-polarity transistor in the second CMOS inverter circuit and the gates of the second-polarity transistor in the first CMOS inverter circuit and the first-polarity transistor in the second CMOS inverter circuit.

8. The latch circuit according to claim 1 , further comprising:

an output part externally outputting an output signal,

wherein the output from the first CMOS inverter circuit is coupled to the input of the third CMOS inverter circuit,

wherein the output from the second CMOS inverter circuit is coupled to the input of the fourth CMOS inverter circuit,

wherein the output from the third CMOS inverter circuit is coupled to the input of an output circuit making up the output part and the input of the first CMOS inverter circuit, and

wherein the output from the fourth CMOS inverter circuit is coupled to the input of the output circuit and the input of the second CMOS inverter circuit.