PIXEL CIRCUIT AND ORGANIC LIGHT EMITTING DISPLAY APPARATUS INCLUDING THE SAME
A pixel circuit includes: a second NMOS transistor coupled to a data line and a scan line, the second NMOS transistor for supplying data signals to a first node; a capacitor having a first terminal coupled to the first node and a second terminal coupled to a second node; an OLED having a first terminal coupled to the second node and a second terminal coupled to a second power source; a first NMOS transistor including a first electrode, a second electrode, and a gate electrode coupled to the first node, and for supplying a current corresponding to a voltage applied to the first node from a first power source to the second power source via the OLED; and a third NMOS transistor coupled to the first NMOS transistor in series and configured to be turned on when a light emission control signal is supplied from a light emission control line.
1 . A pixel circuit of an organic light emitting display, the pixel circuit comprising:
a second N-channel metal oxide semiconductor (NMOS) transistor coupled to a data line and a scan line, the second NMOS transistor being for supplying data signals to a first node;
a storage capacitor having a first terminal coupled to the first node and a second terminal coupled to a second node;
an organic light emitting diode (OLED) having a first terminal coupled to the second node and a second terminal coupled to a second power source;
a first NMOS transistor comprising a first electrode, a second electrode, and a gate electrode coupled to the first node, and for supplying a current corresponding to a voltage applied to the first node from a first power source to the second power source via the OLED; and
a third NMOS transistor coupled to the first NMOS transistor in series and configured to be turned on when a light emission control signal is supplied from a light emission control line.
2 . The pixel circuit of claim 1 , wherein the first electrode of the first NMOS transistor is a drain electrode and the second electrode of the first NMOS transistor is a source electrode, and the second electrode of the first NMOS transistor is coupled to the second node.
3 . The pixel circuit of claim 1 , wherein the third NMOS transistor comprises:
a gate electrode coupled to the light emission control line;
a first electrode coupled to the first power source; and
a second electrode coupled to the first electrode of the first NMOS transistor.
4 . The pixel circuit of claim 1 , wherein the third NMOS transistor comprises:
a gate electrode coupled to the light emission control line;
a first electrode coupled to the second electrode of the first NMOS transistor; and
a second electrode coupled to the second node.
5 . The pixel circuit of claim 1 , wherein the second NMOS transistor is configured to be turned on when a scan signal is supplied from the scan line.
6 . The pixel circuit of claim 1 , further comprising a third power source for applying a reference voltage to the second node.
7 . The pixel circuit of claim 1 , wherein the first power source is configured to supply a first voltage, and the second power source is configured to supply a second voltage that is lower than the first voltage.
8 . An organic light emitting display apparatus comprising:
a first scan driver coupled to light emission control lines for supplying light emission control signals;
a second scan driver coupled to scan lines for supplying scan signals;
a data driver coupled to data lines for supplying data signals; and
a display unit comprising a plurality of pixel circuits coupled to the scan lines, the light emission control lines, and the data lines,
wherein each of the pixel circuits comprises:
a second N-channel metal oxide semiconductor (NMOS) transistor for supplying a corresponding one of the data signals to a first node, the second NMOS transistor coupled to a corresponding one of the data lines and a corresponding one of the scan lines;
a storage capacitor having a first terminal coupled to the first node and a second terminal coupled to a second node;
an organic light emitting diode (OLED) having a first terminal coupled to the second node and a second terminal coupled to a second power source;
a first NMOS transistor comprising a first electrode, a second electrode, and a gate electrode coupled to the first node, and for supplying a current corresponding to a voltage applied to the first node from a first power source to the second power source via the OLED; and
a third NMOS transistor coupled to the first NMOS transistor in series and configured to be turned on when a corresponding one of the light emission control signals is supplied from a corresponding one of the light emission control lines.
9 . The organic light emitting display apparatus of claim 8 , wherein the first electrode of the first NMOS transistor is a drain electrode and the second electrode of the first NMOS transistor is a source electrode, and the second electrode of the first NMOS transistor is coupled to the second node.
10 . The organic light emitting display apparatus of claim 8 , wherein the third NMOS transistor comprises:
a gate electrode coupled to the corresponding light emission control line;
a first electrode coupled to the first power source; and
a second electrode coupled to the first electrode of the first NMOS transistor.
11 . The organic light emitting display apparatus of claim 8 , wherein the third NMOS transistor comprises:
a gate electrode coupled to the corresponding one of the light emission control lines;
a first electrode coupled to the second electrode of the first NMOS transistor; and
a second electrode coupled to the second node.
12 . The organic light emitting display apparatus of claim 8 , wherein the second NMOS transistor is configured to be turned on when a corresponding one of the scan signals is supplied from a corresponding one of the scan lines.
13 . The organic light emitting display apparatus of claim 8 , further comprising a third power source for applying a reference voltage to the second node.
14 . The organic light emitting display apparatus of claim 8 , wherein the first power source is configured to apply a first voltage, and the second power source is configured to apply a second voltage that is lower than the first voltage.