IP Library Granted Patent US 8,012,837
Granted Patent B2
US 8,012,837 · App. 12/716,403 · Granted Sep 6, 2011

Method of manufacturing semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,012,837
App. No.
12/716,403
Granted
Sep 6, 2011
Kind
B2
Abstract

A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

Claims (15)

1. A method of manufacturing a semiconductor device, comprising:

growing epitaxially a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate;

polishing a surface of the silicon carbide semiconductor layer;

ion-implanting impurities into the silicon carbide semiconductor layer after the polishing;

performing a heat treatment to activate the impurities;

forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the performing the heat treatment;

removing chemically the first thermal oxide film; and

forming an electrode layer on the silicon carbide semiconductor film.

2. The method according to claim 1 , wherein the polishing is performed by chemical mechanical polishing (CMP).

3. The method according to claim 2 , wherein an amount of polishing of the silicon carbide semiconductor layer is 4 μm or more.

4. The method according to claim 1 , further comprising forming a second thermal oxide film on the surface of the silicon carbide semiconductor layer between the polishing and the ion-implanting.

5. The method according to claim 1 , wherein the forming the first thermal oxide film is performed in an atmosphere containing water vapor.

6. The method according to claim 1 , further comprising performing shape inspection for the surface of the silicon carbide semiconductor layer after the polishing and before the ion-implanting impurities.

7. The method according to claim 1 , wherein a growth film thickness in the growing epitaxially the silicon carbide semiconductor layer is set to a film thickness obtained by adding a thickness expected to reduce in the polishing to a designed film thickness of the semiconductor device.

8. The method according to claim 4 , wherein the forming the second thermal oxide film is performed in an atmosphere containing water vapor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2010
From: NISHIO, JOHJI; OTA, CHIHARU; SUZUKI, TAKUMA; KONO, HIROSHI; MIZUKAMI, MAKOTO; SHINOHE, TAKASHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024239/0891 →
Priority Claims (1)
JP 2009-207940 · Sep 9, 2009 · national
Continuity (1)
Related Publication 20110059597A1 · Mar 10, 2011