System for Simulating Processor Power Consumption and Method of the Same

1 . A method for simulating processor power consumption, the method comprising:

simulating a simulated processor by a simulation module;

utilizing a power analysis model to analyze said simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of said at least one fragment by a analysis module;

computing at least one power correction factor between said plurality of basic blocks by a correction module;

utilizing a processing apparatus to generate a simulation model with power annotation based on said power analysis and said at least one power correction factor by a annotation module; and

predicting power consumption of said simulated processor based on said simulation model with power annotation by a prediction module.

2 . The method according to claim 1 , wherein said power analysis model is architecture level power analysis model.

3 . The method according to claim 1 , wherein said power correction factor comprises pipeline, branch, or cache miss power correction factor.

4 . The method according to claim 1 , further comprising a step of cross compilation, for generating target binary code.

5 . The method according to claim 1 , further comprising a step of power analysis utilizing breadth first search algorithm.

6 . A storage medium readable by a processor, storing instructions executable by said processor to perform a method for simulating processor power consumption, said method comprising:

simulating a simulated processor by a simulation module;

utilizing a power analysis model to analyze said processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of said at least one fragment by a analysis module;

computing at least one power correction factor between said plurality of basic blocks by a correction module;

utilizing a processing apparatus to generate a simulation model with power annotation based on said power analysis and said at least one power correction factor by a annotation module; and

predicting power consumption of said simulated processor based on said simulation model with power annotation by a prediction module.

7 . The storage medium according to claim 6 , wherein said power analysis model is architecture level power analysis model.

8 . The storage medium according to claim 6 , wherein said power correction factor comprises pipeline, branch, or cache miss power correction factor.

9 . The storage medium according to claim 6 , wherein said method further comprises a step of cross compilation, for generating target binary code.

10 . The storage medium according to claim 6 , wherein said method further comprises a step of power analysis utilizing breadth first search algorithm.

11 . A software product, tangibly embedded in a computer readable storage medium, for simulating processor power consumption, the software product comprising instructions operable to cause a processing apparatus to perform a method for

simulating processor power consumption, the method comprising:

simulating a simulated processor by a simulation module;

utilizing a power analysis model to analyze said simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of said at least one fragment by a analysis module;

computing at least one power correction factor between said plurality of basic blocks by a correction module;

generating a simulation model with power annotation based on said power analysis and said at least one power correction factor by a annotation module; and

predicting power consumption of said simulated processor based on said simulation model with power annotation by a prediction module.

12 . The software product according to claim 11 , wherein said power analysis model is architecture level power analysis model.

13 . The software product according to claim 11 , wherein said power correction factor comprises pipeline, branch, or cache miss power correction factor.

14 . The software product according to claim 11 , further comprising instructions operable to cause said processing processor to perform a step of cross compilation, for generating target binary code.

15 . The software product according to claim 11 , further comprising instructions operable to cause said processing processor to perform a step of power analysis utilizing breadth first search algorithm.

16 . A system for simulating processor power consumption, the system comprising:

a control module;

a simulation module, coupled to said control module, for simulating a simulated processor;

an analysis module, coupled to said control module, for utilizing a power analysis model to analyze said simulated processor's execution of at least one fragment of a target program and generate power analysis of a plurality of basic blocks of said at least one fragment;

a correction module, coupled to said control module, for computing at least one power correction factor between said plurality of basic blocks;

an annotation module, coupled to said control module, for generating a simulation model with power annotation based on said power analysis and said at least one power correction factor; and

a prediction module, coupled to said control module, for predicting power consumption of said simulated processor based on said simulation model with power annotation.

17 . The system according to claim 16 , wherein said power analysis model is architecture level power analysis model.

18 . The system according to claim 16 , wherein said correction module is configured to provide power correction factor of pipeline, branch, or cache miss.

19 . The system according to claim 16 , wherein said analysis model is configured to utilize a cross compiler to cross compile, for generating target binary code.

20 . The system according to claim 16 , wherein said analysis module is configured to utilize breadth first search algorithm for power analysis.