IP Library Granted Patent US 8,367,479
Granted Patent B2
US 8,367,479 · App. 12/718,200 · Granted Feb 5, 2013

Semiconductor device and manufacturing method thereof

Inventors: Hiroyuki Nakamura (Tokyo, JP); Akira Muto (Tokyo, JP); Nobuya Koike (Tokyo, JP); Atsushi Nishikizawa (Tokyo, JP); Yukihiro Sato (Tokyo, JP); Katsuhiko Funatsu (Tokyo, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,367,479
App. No.
12/718,200
Granted
Feb 5, 2013
Kind
B2
Abstract

To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.

Claims (34)

1. A manufacturing method of a semiconductor device, comprising the steps of:

(a) preparing a lead frame having a die pad and a plurality of lead portions;

(b) surface-roughening the lead frame partially;

(c) bonding a semiconductor chip onto the top surface of the die pad via a die bonding material; and

(d) sealing, with an insulating resin, an inner lead portion of each of the lead portions, a portion of the die pad, and the semiconductor chip,

wherein in the step (b), etching is performed while covering a portion of the lead frame with a protecting member to roughen the surface of another portion not covered with the protecting member,

wherein in the step (b), a portion of the die pad to be brought into contact with the insulating resin used for sealing in the step (d) is surface-roughened;

wherein in the step (b), a second main surface of the die pad which is located on the side opposite to the first main surface in a thickness direction is not surface-roughened,

wherein in the step (b), an outer lead portion of each of the lead portions is not surface-roughened, and

wherein in the step (d), sealing with the insulating resin is performed so as to expose the bottom surface of the die pad.

2. The manufacturing method of a semiconductor device according to claim 1 ,

wherein in the step (b), the inner lead portion is not surface-roughened.

3. The manufacturing method of a semiconductor device according to claim 1 ,

wherein in the step (a), the lead frame includes a conductor having, as a main component thereof, copper, and

wherein in the step (a), the inner lead portion is plated with a conductor having, as a main component thereof, nickel.

4. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the lead frame prepared in the step (a) has a suspension lead portion for supporting the die pad therewith,

wherein in the step (b), the suspension lead portion is covered with a protecting member to prevent the surface roughening,

wherein in the step (d), the suspension lead portion is sealed with the insulating resin so as to expose a portion thereof, and

wherein the manufacturing method further comprises, after the step (d), a step of cutting a portion of the suspension lead portion not sealed with the insulating resin.

5. The manufacturing method of a semiconductor device according to claim 1 ,

wherein in the step (b), the lead frame is partially surface-roughened so that an area of a portion of the surface-roughened die pad to be brought into contact with the insulating resin used for sealing in the step (d) is greater than an area of a portion of the semiconductor chip to be brought into contact with the insulating resin.

6. The manufacturing method of a semiconductor device according to claim 1 ,

wherein in the step (b), the lead frame is partially surface-roughened by etching with an etching solution having, as a main component thereof, a mixed solution of hydrogen peroxide water and sulfuric acid.

7. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the protecting member used in the step (b) is a masking tape.

8. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the semiconductor chip to be bonded to a first main surface of the die pad in the step (c) has an electrode on a surface to which the die pad is bonded via the die bonding material, and

wherein the die bonding material to be used in the step (c) is a solder material having conductivity.

9. The manufacturing method of a semiconductor device according to claim 1 ,

wherein the die bonding material to be used in the step (c) is a resin paste material, and

wherein in the step (b), a portion of the die pad which the semiconductor chip is bonded to and the die bonding material is brought into contact with in the step (c) is surface-roughened.

10. The manufacturing method of a semiconductor device according to claim 1 ,

wherein after the step (b), the upper surface of the die pad has thereon convexities and concavities of from 0.2 to 0.5 μm in terms of an arithmetic average roughness.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER AND CHANGE OF NAME Recorded Jul 29, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024755/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2010
From: NAKAMURA, HIROYUKI; MUTO, AKIRA; KOIKE, NOBUYA; NISHIKIZAWA, ATSUSHI; SATO, YUKIHIRO; FUNATSU, KATSUHIKO
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 024034/0605 →
Priority Claims (1)
JP 2009-094648 · Apr 9, 2009 · national
Continuity (1)
Related Publication 20100258922A1 · Oct 14, 2010