IP Library Granted Patent US 8,458,377
Granted Patent B2
US 8,458,377 · App. 12/718,279 · Granted Jun 4, 2013

DMA engine capable of concurrent data manipulation

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Quick Facts
Patent No.
US 8,458,377
App. No.
12/718,279
Granted
Jun 4, 2013
Kind
B2
Abstract

Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption. The data modification engines that perform the data manipulation operations may be implemented on the DMA controller such that the use of memory during data manipulation operations uses local RAM so as to avoid a need to access external memory during data manipulation operations.

Claims (36)

1. A method to perform a plurality of data modification operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller comprising:

providing a plurality of data modification engines within said DMA controller that each perform at least one of a variety of data modification operations;

fetching a Control Data Block (CDB) by said DMA controller, said CDB containing instructions for reading said data from at least one data source, performing said plurality of data modification operations on said data, and writing said data to at least one destination;

retrieving by said DMA controller said data from at least one data source in accord with said instructions encoded in said CDB;

performing within said DMA controller each data modification operation of said plurality of data modification operations on said data received by said DMA controller using one of said plurality of data modification engines provided on said DMA controller for each data modification operation in accord with said instructions encoded in said CDB such that at least two of said plurality of data modification operations are performed concurrently by said DMA controller and a first data modification engine of said plurality of data modification engines creates first data results that are used as a basis of computation for a second data modification engine of said plurality of data modification engines to perform at least one data modification operation of said plurality of data modification operations; and

sending by said DMA controller results of said plurality of data modification operations to at least one destination in accord with said instructions encoded in said CDB.

2. The method of claim 1 wherein said retrieving of said data from said at least one data source further comprises:

creating read commands within said DMA controller in accord with said instructions encoded in said CDB to read said data from said at least one data source;

sending said read commands from said DMA controller to said at least one data source; and

receiving at said DMA controller said data from said at least one data source sent by said at least one data source in accord with said read commands.

3. The method of claim 1 wherein said sending of said results of said plurality of data modification operations to at least one destination further comprises:

creating write commands within said DMA controller in accord with said instructions encoded in said CDB to write said results of said plurality of data modification operations to said at least one destination; and

sending by said DMA controller said results of said plurality of data modification operations to said at least one destination in accord with said write commands.

4. The method of claim 1 further comprising storing said data retrieved by said DMA controller in an electronic memory that is included locally within said DMA controller.

5. The method of claim 1 further comprising storing said results of said plurality of data modification operations in an electronic memory that is included locally within said DMA.

6. The method of claim 1 wherein each data modification engine of said plurality performs at least one data modification operation of a group of data modification operations comprising: hash, Hash Message Authentication Code (HMAC), hash/HMAC combined, fill pattern, Linear Feedback Shift Register (LFSR), End-to-End Data Protection (EEDP) check, EEDP add, EEDP update, EEDP remove, exclusive OR (XOR), encryption, and decryption.

7. The method of claim 1 wherein said plurality of data modification engines is comprised of at least two of a single type of data modification operation such that said single type of data modification operation may be performed concurrently on said DMA controller.

8. The method of claim 1 wherein said sending of said results of said plurality of data modification operations to at least one destination further sends said original data retrieved by said DMA controller to said at least one data destination.

9. A Direct Memory Access (DMA) controller that performs a plurality of data modification operations on data being transferred via a Direct Memory Access (DMA) channel managed by said DMA controller comprising:

a Control Data Block (CDB) processor subsystem that fetches a Control Data Block (CDB), said CDB containing instructions for reading said data from at least one data source, performing said plurality of data modification operations on said data, and writing said data to at least one destination;

a fill subsystem that retrieves said data from at least one data source in accord with said instructions encoded in said CDB;

a plurality of data modification engines within said DMA controller that each perform at least one of a variety of data modification operations for each data modification operation of said plurality of data modification operations on said data received by fill subsystem in accord with said instructions encoded in said CDB such that at least two of said plurality of data modification operations are performed concurrently by said DMA controller and a first data modification engine of said plurality of data modification engines creates first data results that are used as a basis of computation for a second data modification engine of said plurality of data modification engines to perform at least one data modification operation of said plurality of data modification operations; and

a drain subsystem that sends results of said plurality of data modification operations to at least one destination in accord with said instructions encoded in said CDB.

10. The DMA controller of claim 9 wherein said fill subsystem retrieves said data from said at least one data source by creating read commands in accord with said instructions encoded in said CDB to read said data from said at least one data source, sending said read commands to said at least one data source, and receiving said data from said at least one data source sent by said at least one data source in accord with said read commands.

11. The DMA controller of claim 9 wherein said drain subsystem sends said results of said plurality of data modification operations to at least one destination by creating write commands in accord with said instructions encoded in said CDB to write said results of said plurality of data modification operations to said at least one destination and sending said results of said plurality of data modification operations to said at least one destination in accord with said write commands.

12. The DMA controller of claim 9 further comprising a source data storage that stores said data retrieved by said fill subsystem, said source data storage being an electronic memory that is included locally within said DMA controller.

13. The DMA controller of claim 9 further comprising at least one modify data storage that stores said results of said plurality of data modification operations, said at least one modify data storage being an electronic memory that is included locally within said DMA.

14. The DMA controller of claim 9 wherein each data modification engine of said plurality performs at least one data modification operation of a group of data modification operations comprising: hash, Hash Message Authentication Code (HMAC), hash/HMAC combined, fill pattern, Linear Feedback Shift Register (LFSR), End-to-End Data Protection (EEDP) check, EEDP add, EEDP update, EEDP remove, exclusive OR (XOR), encryption, and decryption.

15. The DMA controller of claim 9 wherein said plurality of data modification engines is comprised of at least two of a single type of data modification operation such that said single type of data modification operation may be performed concurrently on said DMA controller.

16. The DMA controller of claim 9 wherein said drain subsystem further sends said original data retrieved by said DMA controller to said at least one data destination.

17. A Direct Memory Access (DMA) controller that performs a plurality of data modification operations on data being transferred via a Direct Memory Access (DMA) channel managed by said DMA controller comprising:

means for providing a plurality of data modification engines within said DMA controller that each perform at least one of a variety of data modification operations;

means for fetching a Control Data Block (CDB) by said DMA controller, said CDB containing instructions for reading said data from at least one data source, performing said plurality of data modification operations on said data, and writing said data to at least one destination;

means for retrieving by said DMA controller said data from at least one data source in accord with said instructions encoded in said CDB;

means for performing within said DMA controller each data modification operation of said plurality of data modification operations on said data received by said DMA controller using one of said plurality of data modification engines provided on said DMA controller for each data modification operation in accord with said instructions encoded in said CDB such that at least two of said plurality of data modification operations are performed concurrently by said DMA controller and a first data modification engine of said plurality of data modification engines creates first data results that are used as a basis of computation for a second data modification engine of said plurality of data modification engines to perform at least one data modification operation of said plurality of data modification operations; and

means for sending by said DMA controller results of said plurality of data modification operations to at least one destination in accord with said instructions encoded in said CDB.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2010
From: PICCIRILLO, GARY; OLSON, DAVID M.
To: LSI CORPORATION
Reel/Frame 024145/0525 →