IP Library › Granted Patent US 8,487,643

Granted Patent B2

US 8,487,643 · App. 12/718,451 · Granted Jul 16, 2013

Substrate with test circuit

Inventors: Yupeng Chen (Beijing, CN); Hua Liu (Beijing, CN); Haoran Gao (Beijing, CN); Yu Lu (Beijing, CN)

Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.

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Quick Facts

Patent No.: US 8,487,643
App. No.: 12/718,451
Filed: Mar 5, 2010
Granted: Jul 16, 2013
Kind: B2
Examiner: BENITEZ ROSARIO, JOSHUA
Art Unit: 2858
USPC: 324/760.01

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

The present invention relates to a substrate with a substrate test circuit. In an embodiment, by making the length of the wiring from a first data-line-test input terminal to a first panel equal to that of the wiring from a second data-line-test input terminal to the first panel, the input resistances between two test input terminals of a first data-line-test line and the first panel are identical, and thus when a data line of the first panel is detected, the voltage drops of test signals inputted from the two test input terminals are the same, and the test signals actually loaded to the first panel are the same and the detecting abilities are identical.

Claims (81)

1. A substrate comprising at least one exposure unit disposed at a transverse direction and a substrate test circuit, wherein the substrate test circuit comprises:

a first data-line-test line, a first gate-line-test line and a first common-electrode-line-test line, which are connected with a first panel within a single exposure unit,

wherein the first data-line-test line comprises a first data-line-test input terminal and a second data-line-test input terminal, which are disposed on both sides of the exposure unit,

the first gate-line-test line comprises a first gate-line-test input terminal and a second gate-line-test input terminal, which are disposed on both sides of the exposure unit,

the first common-electrode-line-test line comprises a first common-electrode-line-test input terminal and a second common-electrode-line-test input terminal, which are disposed on both sides of the exposure unit,

the first data-line-test input terminal, the first gate-line-test input terminal and the first common-electrode-line-test input terminal are disposed on the same side of the exposure unit,

a length of a wiring from the first data-line-test input terminal to the first panel is the same as a length of a wiring from the second data-line-test input terminal to the first panel;

a length of a wiring from the first gate-line-test input terminal to the first panel is the same as a length of a wiring from the second gate-line-test input terminal to the first panel; and

a length of a wiring from the first common-electrode-line-test input terminal to the first panel is the same as a length of a wiring from the second common-electrode-line-test input terminal to the first panel,

wherein at least one of the wiring from the first data-line-test input terminal to the first panel and the wiring from the second data-line-test input terminal to the first panel, at least one of the wiring from the first gate-line-test input terminal to the first panel and the wiring from the second gate-line-test input terminal to the first panel and at least one of the wiring from the first common-electrode-line-test input terminal to the first panel and the wiring from the second common-electrode-line-test input terminal to the first panel comprise a zigzag route.

2. The substrate of claim 1 , further comprising:

a second data-line-test line, a second gate-line-test line and a second common-electrode-line-test line connected with a second panel within the exposure unit,

wherein the second data-line-test line comprises a third data-line-test input terminal and a fourth data-line-test input terminal, which are disposed on both sides of the exposure unit,

the second gate-line-test line comprises a third gate-line-test input terminal and a fourth gate-line-test input terminal, which are disposed on both sides of the exposure unit,

the second common-electrode-line-test line comprises a third common-electrode-line-test input terminal and a fourth common-electrode-line-test input terminal, which are disposed on both sides of the exposure unit, and

the third data-line-test input terminal, the third gate-line-test input terminal and the third common-electrode-line-test input terminal are disposed on the same side of the exposure unit,

a length of a wiring from the third data-line-test input terminal to the second panel is the same as a length of a wiring from the fourth data-line-test input terminal to the second panel;

a length of a wiring from the third gate-line-test input terminal to the second panel is the same as a length of a wiring from the fourth gate-line-test input terminal to the second panel; and

a length of a wiring from the third common-electrode-line-test input terminal to the second panel is the same as a length of a wiring from the fourth common-electrode-line-test input terminal to the second panel.

3. The substrate of claim 2 , wherein the length of the wiring from the first data-line-test input terminal to the first panel is the same as the length of the wiring from the third data-line-test input terminal to the second panel;

the length of the wiring from the first gate-line-test input terminal to the first panel is the same as the length of the wiring from the third gate-line-test input terminal to the second panel; and

the length of the wiring from the first common-electrode-line-test input terminal to the first panel is the same as the length of the wiring from the third common-electrode-line-test input terminal to the second panel.

4. The substrate of claim 1 , comprising two exposure units in the transverse direction and a plurality of exposure units in a vertical direction, wherein each exposure unit comprising the substrate test circuit.

5. A substrate comprising at least one exposure unit disposed at a transverse direction and a substrate test circuit, wherein the substrate test circuit comprises:

a first data-line-test line connected with a first panel within a single exposure unit, and

a second data-line-test line connected with a second panel within the exposure unit,

wherein the first data-line-test line comprises a first data-line-test input terminal and a second data-line-test input terminal, which are disposed on both sides of the exposure unit,

the second data-line-test line comprises a third data-line-test input terminal and a fourth data-line-test input terminal, which are disposed on both sides of the exposure unit,

the first data-line-test input terminal and the third data-line-test input terminal are disposed on the same side of the exposure unit, and

a length of a wiring from the first data-line-test input terminal to the first panel is the same as a length of a wiring from the second data-line-test input terminal to the first panel;

a length of a wiring from the third data-line-test input terminal to the second panel is the same as a length of a wiring from the fourth data-line-test input terminal to the second panel; and

the length of the wiring from the first data-line-test input terminal to the first panel is the same as the length of the wiring from the third data-line-test input terminal to the second panel,

wherein at least one of the wiring from the first data-line-test input terminal to the first panel, the wiring from the second data-line-test input terminal to the first panel, the wiring from the third data-line-test input terminal to the second panel and the wiring from the fourth data-line-test input terminal to the second panel comprises a zigzag route.

6. The substrate of claim 5 , further comprising:

a first gate-line-test line connected with the first panel, and

a second gate-line-test line connected with the second panel,

wherein the first gate-line-test line comprises a first gate-line-test input terminal and a second gate-line-test input terminal, which are disposed on both sides of the exposure unit,

the second gate-line-test line comprises a third gate-line-test input terminal and a fourth gate-line-test input terminal, which are disposed on both sides of the exposure unit,

the first gate-line-test input terminal and the third gate-line-test input terminal are disposed on the same side of the exposure unit,

a length of a wiring from the first gate-line-test input terminal to the first panel is the same as a length of a wiring from the second gate-line-test input terminal to the first panel;

a length of a wiring from the third gate-line-test input terminal to the second panel is the same as a length of a wiring from the fourth gate-line-test input terminal to the second panel; and

the length of the wiring from the first gate-line-test input terminal to the first panel is the same as the length of the wiring from the third gate-line-test input terminal to the second panel.

7. The substrate test circuit of claim 6 , further comprising:

a first common-electrode-line-test line connected with the first panel, and

a second common-electrode-line-test line connected with the second panel,

wherein the first common-electrode-line-test line comprises a first common-electrode-line-test input terminal and a second common-electrode-line-test input terminal, which are disposed on both sides of the exposure unit,

the first common-electrode-line-test input terminal and the third common-electrode-line-test input terminal are disposed on the same side of the exposure unit,

8. The substrate test circuit of claim 5 , further comprising:

a first common-electrode-line-test line connected with the first panel, and

a second common-electrode-line-test line connected with the second panel,

the first common-electrode-line-test input terminal and the third common-electrode-line-test input terminal are disposed on the same side of the exposure unit,

9. The substrate of claim 5 , comprising two exposure units in the transverse direction and a plurality of exposure units in a vertical direction, wherein each exposure unit comprising the substrate test circuit.

10. A substrate comprising at least one exposure unit disposed at a transverse direction and a substrate test circuit, wherein the substrate test circuit comprises:

a first gate-line-test line connected with a first panel within a single exposure unit, and

a second gate-line-test line connected with a second panel in the exposure unit,

wherein the first gate-line-test line comprises a first gate-line-test input terminal and a second gate-line-test input terminal, which are disposed on both sides of the exposure unit,

the second gate-line-test line comprises a third gate-line-test input terminal and a fourth gate-line-test input terminal , which are disposed on both sides of the exposure unit,

the first gate-line-test input terminal and the third gate-line-test input terminal are disposed on the same side of the exposure unit,

a length of a wiring from the first gate-line-test input terminal to the first panel is the same as a length of a wiring from the second gate-line-test input terminal to the first panel;

a length of a wiring from the third gate-line-test input terminal to the second panel is the same as a length of a wiring from the fourth gate-line-test input terminal to the second panel; and

the length of the wiring from the first gate-line-test input terminal to the first panel is the same as the length of the wiring from the third gate-line-test input terminal to the second panel,

wherein at least one of the wiring from the first gate-line-test input terminal to the first panel, the wiring from the second gate-line-test input terminal to the first panel, the wiring from the third gate-line-test input terminal to the second panel and the wiring from the fourth gate-line-test input terminal to the second panel comprises a zigzag route.

11. The substrate of claim 10 , further comprising:

a first data-line-test line connected with the first panel, and

a second data-line-test line connected with the second panel,

wherein the first data-line-test line comprises a first data-line-test input terminal and a second data-line-test input terminal disposed on both sides of the exposure unit,

the second data-line-test line comprises a third data-line-test input terminal and a fourth data-line-test input terminal disposed on both sides of the exposure unit,

the first data-line-test input terminal and the third data-line-test input terminal are disposed on the same side of the exposure unit,

a length of a wiring from the first data-line-test input terminal to the first panel is the same as a length of a wiring from the second data-line-test input terminal to the first panel;

a length of a wiring from the third data-line-test input terminal to the second panel is the same as a length of a wiring from the fourth data-line-test input terminal to the second panel; and

the length of the wiring from the first data-line-test input terminal to the first panel is the same as the length of the wiring from the third data-line-test input terminal to the second panel.

12. The substrate of claim 10 , comprising two exposure units in the transverse direction and a plurality of exposure units in a vertical direction, wherein each exposure unit comprising the substrate test circuit.

Assignments (2)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2015

From: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD

To: BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO. LTD

Reel/Frame 036644/0601 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2010

From: CHEN, YUPENG; LIU, HUA; GAO, HAORAN; LU, YU

To: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Reel/Frame 024037/0143 →

Priority Claims (1)

CN 2009 1 0079296 · Mar 6, 2009 · national

Continuity (1)

Related Publication 20100224875A1 · Sep 9, 2010