Manufacturing method of semiconductor device
View Patent ↗The semiconductor device si formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thinkness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.
1. A manufacturing method of a semiconductor device comprising the steps of:
(a) forming a first metal film over a first main surface of a semiconductor wafer having a first thickness;
(b) conducting, after the step (a), back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness;
(c) forming, after the step (b), an insulation film pattern comprising a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof;
(d) making the thickness for the opening of the annular insulation film pattern to a third thickness which is thinner than the second thickness in a state where the insulation film pattern is present;
(e) conducting, after the step (d), an electric test to the semiconductor wafer in a state where the insulation film pattern is present;
(f) bonding, after the step (e), the second main surface of the semiconductor wafer to a pressure sensitive adhesive sheet thereby holding the semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present; and
(g) dividing, after the step (f), the semiconductor wafer into individual chips in a state where it is held to the dicing frame.
2. The manufacturing method according to claim 1 , wherein the first insulation film has such a stress as relieving the stress exerting on the semiconductor wafer.
3. The manufacturing method according to claim 1 , wherein the first insulation film is formed by CVD.
4. The manufacturing method according to claim 1 , wherein the first insulation film is formed by plasma CVD.
5. The manufacturing method according to claim 1 , wherein the first insulation film is formed by sputtering.
6. The manufacturing method according to claim 1 , wherein the insulation film pattern shows an annular shape along the outer periphery of the semiconductor wafer.
7. The manufacturing method according to claim 1 , wherein the first insulation film is an inorganic insulation film.
8. The manufacturing method according to claim 1 , wherein, the first insulation film is a silicon nitride type insulation film.
9. The manufacturing method according to claim 1 , wherein the first metal film is an aluminum type, copper type, or tungsten type metal film.
10. The manufacturing method according to claim 1 , wherein the etching in the step (d) is wet etching.
11. The manufacturing method according to claim 1 , wherein the insulation film pattern is formed by sputtering using a shadow mask.
12. The manufacturing method according to claim 1 , wherein the electric test in the step (e) is a wafer test.
13. The manufacturing method according to claim 1 , wherein the semiconductor device comprises a power MOSFET.
14. The manufacturing method according to claim 1 , wherein the semiconductor device comprises an IGBT.
15. The manufacturing method according to claim 1 , wherein the semiconductor wafer is a silicon type wafer.
16. The manufacturing method according to claim 1 , further comprising a step of:
(h) before the step (e) and after the step (d), forming a second metal film over the second main surface of the semiconductor wafer in a state where the insulation film pattern is present.
17. The manufacturing method according to claim 16 , further comprising a step of:
(i) before the step (h) and after the step (d), implanting impurity ions to the second main surface of the semiconductor wafer in a state where the insulation film pattern is present.
18. The manufacturing method according to claim 17 , further comprising a step of:
(j) before the step (h) and after the step (i), conducting activation annealing for the impurity ions to the second main surface of the semiconductor wafer in a state where the insulation film pattern is present.
19. The manufacturing method according to claim 18 , further comprising a step of:
(k) before the step (h) and after the step (j), removing an oxide film in the opening of the second main surface of the semiconductor wafer in a state where the insulation film pattern is present.
20. The manufacturing method according to claim 1 , wherein the first thickness is 230 μm or more and less than 1 mm, the second thickness is 70 μm or more and less than 230 μm, and the third thickness is less than 200 μm and 30 μm or more.