Successive approximation analog/digital converter and time-interleaved successive approximation analog/digital converter
View Patent ↗A successive approximation analog/digital converter includes a sample & hold part sampling and holding an intensity of an analog input signal using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a second comparator comparing the intensity of the analog input signal with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part; a successive approximation register determining a value of an MSB of a digital value to be converted according to the comparison result of the second comparator and values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the comparison voltages using the estimated digital values and the reference voltage.
1. A successive approximation analog/digital converter comprising:
a sample & hold part sampling and holding an intensity of an analog input signal by using a single clock cycle of a clock signal;
a first comparator comparing the intensity of the analog input signal held by the sample & hold part with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part;
a second comparator comparing the intensity of the analog input signal sampled by the sample & hold part with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part;
a successive approximation register determining a value of a most significant bit (MSB) of a digital value to be converted according to the comparison result of the second comparator, determining values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and
a digital/analog converter generating the comparison voltages by using the estimated digital values and the reference voltage.
2. A time-interleaved successive approximation analog/digital converter comprising:
a plurality of analog/digital converters successively operating according to corresponding clock cycles, each of the plurality of analog/digital converters comprising: a sample & hold part sampling and holding an intensity of an analog input signal by using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal held by the sample & hold part with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a successive approximation register determining values of bits successive to a most significant bit (MSB) of a digital value to be converted according to the comparison result of the first comparator and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the comparison voltages by using the estimated digital values and a preset reference voltage;
a second comparator comparing the intensity of the analog input signal with a value equal to ½ of the preset reference voltage in the latter half of the operating clock cycle of the sample & hold part included in each of the plurality of analog/digital converters; and
a switching part transmitting the comparison result of the second comparator to the successive approximation register included in each of the plurality of analog/digital converters according to operating clock cycles of the plurality of corresponding analog/digital converters,
wherein the successive approximation register included in each of the plurality of analog/digital converters determines a value of the MSB of the digital value to be converted according to the comparison result of the second comparator.