PLL/DLL dual loop data synchronization
View Patent ↗A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
1. A method of synchronizing data in a plesiochronous system, comprising:
receiving an input data and a data clock;
writing the input data to a first-in-first out register (FIFO);
monitoring a fill level of the FIFO;
generating a signal by a phase locked loop (PLL) in relation to a phase of a reference signal input to the PLL;
generating a transmit clock by adjusting the phase of the signal generated by the PLL according to the fill level of the FIFO so that a change in the fill level of the FIFO corresponds to a frequency offset in the signal generated by the PLL relative to the phase of reference signal input to the PLL; and
outputting the input data from the FIFO according to the transmit clock.
2. A method of synchronizing data in a plesiochronous system according to claim 1 , wherein monitoring the fill level of the FIFO comprises monitoring the fill level of the FIFO in a delay-locked loop (DLL).
3. A method of synchronizing data in a plesiochronous system according to claim 2 , wherein monitoring the fill level of the FIFO in the delay-locked loop comprises reading the fill level of the FIFO using a phase detector.
4. A method of synchronizing data in a plesiochronous system according to claim 3 , further compromising filtering output of the phase detector with a narrow bandwidth filter adapted to reduce a noise present in a data clock.
5. A method of synchronizing data in a plesiochronous system according to claim 1 , wherein generating the transmit clock comprises:
detecting a phase and a frequency of the reference signal input to the PLL in a phase frequency detector of the PLL;
synthesizing the signal generated by the PLL using a voltage controlled oscillator (VCO) of the PLL;
phase shifting the signal generated by the PLL according to the fill level of the FIFO; and
providing feedback to the phase frequency detector corresponding to the phase shifting imparted on the signal generated by the PLL.
6. A method of synchronizing data in a plesiochronous system according to claim 5 , wherein the PLL is adapted to filter a phase noise generated by the VCO.
7. A method of synchronizing data in a plesiochronous system according to claim 1 , wherein writing the input data to a first-in-first-out register (FIFO) comprises writing the input data to the FIFO according to the data clock.
8. A method of synchronizing data in a plesiochronous system according to claim 7 , wherein writing the input data to the FIFO according to the data clock comprises recovering the data clock from the input data.
9. A method of synchronizing data in a plesiochronous system according to claim 8 , wherein recovering the data clock from the input data comprises:
detecting a local reference;
generating an oscillating signal at a frequency proportional to the local reference;
receiving the input data at a phase detector;
reconstructing the data clock, comprising shifting the phase of the oscillating signal according to the input data; and
outputting the data clock.
10. A method of synchronizing data in plesiochronous system according to claim 9 , further comprising filtering the output of the phase detector with a wideband filter adapted to remove input jitter.
11. A method of synchronizing data in a plesiochronous system according to claim 1 , wherein the phase of the signal generated by the PLL is adjusted so that the fill level of the FIFO remains nearly constant.
12. A method of synchronizing data in a plesiochronous system according to claim 1 , further comprising phase-locking an output of a voltage controller oscillator (VCO) of the PLL to the data clock with a narrowband loop set by a bandwidth of a delay locked loop (DLL).
13. A method of synchronizing data in a plesiochronous system according to claim 12 , wherein the VCO is phase-locked to the reference signal input to the PLL outside of the bandwidth of the DLL.