Multi-gate bandgap engineered memory
Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
1. An integrated circuit memory device, comprising:
a semiconductor body;
a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, with insulating members isolating gates in the series from adjacent gates in the series; and
a charge storage structure on the semiconductor body, the charge storage structure including
dielectric charge trapping locations beneath more than one of the plurality of gates in the series, the charge storage structure including
a multilayer tunnel dielectric structure disposed above the semiconductor body, the tunnel dielectric structure, including
a bottom dielectric layer adjacent the channel having a thickness of less than 2 nanometers and having a hole tunneling barrier height,
a middle dielectric layer having a hole-tunneling-barrier height smaller than that of the bottom dielectric layer and having a thickness less than 3 nanometers, and
a top dielectric layer having a hole tunneling barrier height greater than that of the middle dielectric layer;
a charge storage layer disposed above the tunnel dielectric structure, and
a blocking insulating layer disposed above the charge storage layer;
wherein the semiconductor body includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, the multiple-gate channel region having one of n-type and p-type conductivity.
2. The device of claim 1 , including dielectric charge trapping locations beneath all the gates in the series.
3. The device of claim 1 , wherein the series of gates includes more than two gates, and the charge storage structure includes dielectric charge trapping locations beneath more than two gates in the series of gates having more than two gates.
4. The device of claim 1 , wherein the insulating members isolating the gates in the series have thicknesses less than 30 nm between adjacent gates.
5. The device of claim 1 , wherein the charge storage structure is adapted to trap charge in a dielectric charge trapping location beneath one of the gates in the series of gates to establish a target threshold voltage for a high threshold state; and wherein the tunnel dielectric structure is adapted for Fowler Nordheim FN hole tunneling to the charge trapping layer to lower the threshold voltage by at least 2 volts in less than 100 msec.
6. The device of claim 5 , wherein the tunnel dielectric structure is adapted for Fowler Nordheim FN hole tunneling to the charge trapping layer to lower the threshold voltage from the target threshold voltage by about 2 Volts in about 50 msec or less.
7. The device of claim 5 , wherein the tunnel dielectric structure is adapted for Fowler Nordheim FN hole tunneling to the charge trapping layer to lower the threshold voltage from the target threshold voltage by about 6 Volts in about 100 msec or less.
8. The device of claim 1 , wherein the gates in the plurality of gates comprise a material having a word function greater than n-type polysilicon.
9. The device of claim 1 , wherein the gates in the plurality of gates comprise p-type silicon.
10. The device of claim 1 , wherein the gates in the plurality of gates comprise platinum.
11. The device of claim 5 , wherein the bottom dielectric layer has a thickness less than that of the middle dielectric layer.
12. The device of claim 5 , wherein the middle dielectric layer has a thickness such that an electric field applied during FN hole tunneling is sufficient to substantially eliminate the hole tunneling barrier of the middle dielectric layer and the top dielectric layer of the tunnel dielectric structure.
13. The device of claim 5 , wherein the bottom dielectric layer comprises silicon dioxide, the middle dielectric layer comprises silicon nitride, the top dielectric layer comprises silicon dioxide, the charge storage layer comprises silicon nitride and the insulating layer comprises silicon dioxide.
14. The device of claim 13 , wherein the gate comprises p-type silicon.
15. The device of claim 1 , wherein the charge storage layer comprises a dielectric charge trapping layer on the top dielectric layer of the tunnel dielectric structure having a hole tunneling barrier height less than that of the top dielectric layer, and having a thickness greater than about 5 nm; and the insulating layer comprising a blocking dielectric layer on the charge trapping layer having a hole tunneling barrier height greater than that of the dielectric charge trapping layer, and having a thickness greater than 5 nm.
16. The device of claim 1 , wherein the thickness of the bottom dielectric layer is less than or equal to 18 Angstroms.
17. The device of claim 1 , wherein the thickness of the bottom dielectric layer is less than or equal to 15 Angstroms.
18. The device of claim 1 , wherein the thickness of the middle dielectric layer is greater than the thickness of the bottom dielectric layer.
19. The device of claim 15 , wherein the dielectric charge trapping layer thickness is between about 50 Angstroms and about 100 Angstroms.
20. The device of claim 15 , wherein the blocking dielectric layer has a thickness between about 50 Angstroms and about 120 Angstroms.
21. The device of claim 1 , wherein the bottom dielectric layer comprises silicon dioxide, the middle dielectric layer comprises silicon nitride, and the top dielectric layer comprises silicon dioxide.
22. The device of claim 15 , wherein the dielectric charge trapping layer comprises silicon nitride and the blocking dielectric layer comprises silicon dioxide.
23. The device of claim 15 , wherein the gates in the plurality of gates comprise p-type silicon.
24. The device of claim 15 , wherein the gates in the plurality of gates comprise platinum.
25. The device of claim 15 , including bias structures arranged to apply a negative voltage of about 20 Volts or less, across a gate in the plurality of gates and the channel to induce FN hole tunneling sufficient to decrease a threshold voltage by at least 2 Volts in less than 100 msec.
26. The device of claim 15 , including bias structures arranged to apply a negative voltage of about 20 Volts or less, across a gate in the plurality of gates and the channel to induce FN hole tunneling sufficient to decrease a threshold voltage by at least 2 Volts in less than 10 msec.