Integrated circuit comprising a gradually doped bipolar transistor and corresponding fabrication process
View Patent ↗An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4 a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
1. A method for making an integrated circuit comprising:
forming a collector of a bipolar transistor in an upper layer of a substrate by implanting at least one dopant species to form a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone between the central zone and the lateral zone; and
as a result of forming the collector, forming a lower layer of the substrate underlying the collector to have a lightly doped lateral zone and a highly doped central zone, with dopant species in the central zone being electrically inactive.
2. A method according to claim 1 , wherein implanting is performed at an angle of 0°.
3. A method according to claim 1 , further comprising forming a dopant absorbing layer above the collector.
4. A method according to claim 3 , wherein the dopant absorbing layer has at least one aperture to permit implanting therethrough.
5. A method according to claim 1 , wherein the lightly doped intermediate zone has a dopant concentration within a range of 10 16 atoms/cm 3 to 10 19 atoms/cm 3 .
6. A method according to claim 1 , wherein the very lightly doped central zone has a dopant concentration within a range of 10 15 atoms/cm 3 to 10 17 atoms/cm 3 .
7. A method according to claim 1 , wherein the highly doped lateral zone has a dopant concentration within a range of 10 20 to 10 21 atoms/cm 3 .
8. A method for making an integrated circuit comprising:
forming a bipolar transistor comprising a collector in an upper layer of a substrate so that the collector has a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone between the central zone and the lateral zone; and
forming a lower layer of the substrate underlying the collector to have a lightly doped lateral zone and a highly doped central zone, with dopant in the central zone being electrically inactive.
9. A method according to claim 8 , further comprising forming a dopant absorbing layer above the collector.
10. A method according to claim 9 , wherein the dopant absorbing layer has at least one aperture to permit implanting therethrough.
11. A method according to claim 8 , wherein the lightly doped intermediate zone has a dopant concentration within a range of 10 16 atoms/cm 3 to 10 19 atoms/cm 3 .
12. A method according to claim 8 , wherein the very lightly doped central zone has a dopant concentration within a range of 10 15 atoms/cm 3 to 10 17 atoms/cm 3 .
13. A method according to claim 8 , wherein the highly doped lateral zone has a dopant concentration within a range of 10 20 to 10 21 atoms/cm 3 .
14. A method for making an integrated circuit comprising:
providing a silicon-on-insulator substrate comprising an insulator layer and a silicon layer thereon; and
forming a bipolar transistor comprising a collector in the silicon layer so that the collector has a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone between the central zone and the lateral zone; and with the insulating layer underlying the collector having a lightly doped lateral zone and a highly doped central zone, with dopant in the central zone being electrically inactive.
15. A method according to claim 14 , further comprising forming a dopant absorbing layer above the collector.
16. A method according to claim 15 , wherein the dopant absorbing layer has at least one aperture to permit implanting therethrough.
17. A method according to claim 14 , wherein the lightly doped intermediate zone has a dopant concentration within a range of 10 16 atoms/cm 3 to 10 19 atoms/cm 3 .
18. A method according to claim 14 , wherein the very lightly doped central zone has a dopant concentration within a range of 10 15 atoms/cm 3 to 10 17 atoms/cm 3 .
19. A method according to claim 14 , wherein the highly doped lateral zone has a dopant concentration within a range of 10 20 to 10 21 atoms/cm 3 .
20. A method for making an integrated circuit comprising:
providing a substrate comprising a lower layer and an upper layer thereon; and
forming a bipolar transistor comprising a collector in the upper layer of the substrate, the collector comprising a lateral zone with a first dopant concentration, a central zone with a second dopant concentration and an intermediate zone with a third dopant concentration between the central zone and the lateral zone; and with the lower layer of the substrate comprising a lateral zone with a fourth dopant concentration and a central zone with a fifth dopant concentration, with dopant in the central zone being electrically inactive.
21. A method according to claim 20 , wherein the third dopant concentration is within a range of 10 16 atoms/cm 3 to 10 19 atoms/cm 3 .
22. A method according to claim 20 , wherein the fifth dopant concentration is within a range of 10 15 atoms/cm 3 to 10 17 atoms/cm 3 , and the fourth dopant concentration is within a range of 10 20 to 10 21 atoms/cm 3 .
23. A method according to claim 20 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate, with the lower layer of the substrate being the insulator portion thereof.