Method of fabricating a semiconductor device that limits damage to elements of the semiconductor device that are exposed during processing
View Patent ↗A wafer structure ( 88 ) includes a device wafer ( 20 ) and a cap wafer ( 60 ). Semiconductor dies ( 22 ) on the device wafer ( 20 ) each include a microelectronic device ( 26 ) and terminal elements ( 28, 30 ). Barriers ( 36, 52 ) are positioned in inactive regions ( 32, 50 ) of the device wafer ( 20 ). The cap wafer ( 60 ) is coupled to the device wafer ( 20 ) and covers the semiconductor dies ( 22 ). Portions ( 72 ) of the cap wafer ( 60 ) are removed to expose the terminal elements ( 28, 30 ). The barriers ( 36, 52 ) may be taller than the elements ( 28, 30 ) and function to prevent the portions ( 72 ) from contacting the terminal elements ( 28, 30 ) when the portions ( 72 ) are removed. The wafer structure ( 88 ) is singulated to form multiple semiconductor devices ( 89 ), each device ( 89 ) including the microelectronic device ( 26 ) covered by a section of the cap wafer ( 60 ) and terminal elements ( 28, 30 ) exposed from the cap wafer ( 60 ).
1. A method of fabricating a semiconductor device comprising:
forming a semiconductor dies on a side of a device wafer, each of said semiconductor dies including a microelectronic device and a terminal element in electrical communication with said microelectronic device, said terminal element being a bond pad, and an inactive region of said device wafer separates a first bond pad of a first one of said semiconductor dies from a second bond pad of a second one of said semiconductor dies;
positioning a barrier in an inactive region of said device wafer, wherein said barrier does not contact said first and second bond pads;
coupling a cap wafer to said device wafer to form a wafer structure, said cap wafer covering said semiconductor die; and
removing a portion of said cap wafer to expose said terminal element, wherein said barrier substantially prevents said portion from contacting said terminal element when said portion of said cap wafer is removed.
2. A method as claimed in claim 1 wherein:
said forming said multiple semiconductor dies includes forming said terminal element having a first height above a surface of said device wafer; and
said positioning said barrier includes forming said barrier having a second height above said surface of said device wafer, said second height being greater than said first height.
3. A method as claimed in claim 2 wherein said forming and said positioning operations comprise:
depositing a first structural layer on said device wafer;
forming said terminal element and a first layer of said barrier in said first structural layer, wherein said first height of said element corresponds to a depth of said first structural layer;
depositing a second structural layer on said device wafer; and
forming a second layer of said barrier in said second structural layer, said second layer overlying said first layer to produce said second height of said barrier.
4. A method as claimed in claim 2 wherein said second height is at least fifty percent greater than said first height.
5. A method as claimed in claim 1 wherein said forming operation forms multiple conductive lines in electrical communication with said microelectronic device.
6. A method as claimed in claim 5 wherein said positioning operation positions another barrier in each of multiple inactive regions between pairs of said multiple conductive lines.
7. A method as claimed in claim 1 wherein said inactive region is a first inactive region, said barrier is a first barrier, and said method further comprises positioning a second barrier in a second inactive region of said device wafer.
8. A method as claimed in claim 7 further comprising:
forming each of said first and second barriers such that said second barrier is separated from said first barrier by a distance; and
said removing operation removes said portion of said cap wafer as a sliver exhibiting a length, said length being greater than said distance.
9. A method as claimed in claim 1 wherein:
said positioning operation positions said barrier lengthwise oriented in a first direction on a surface of said device wafer; and
said removing operation comprises sawing said cap wafer to remove said portion of said cap wafer, said sawing occurring in a second direction parallel to said surface of said device wafer and substantially perpendicular to said first direction.
10. A method as claimed in claim 1 further comprising singulating said wafer structure to produce multiple semiconductor devices, each of said semiconductor devices including a portion of said device wafer having at least one of said semiconductor dies formed thereon and a section of said cap wafer covering part of said at least one semiconductor die with said terminal element being exposed from said cap wafer.
11. A method of fabricating a semiconductor device comprising:
forming multiple semiconductor dies on a side of a device wafer, each of said semiconductor dies including a microelectronic device and multiple terminal elements in electrical communication with said microelectronic device, said multiple terminal elements being formed as bond pads having a first height above a surface of said device wafer; and an inactive region of said device wafer separates a first set of said bond pads for a first one of said semiconductor dies from a second set of said bond pads for a second one of said semiconductor dies;
positioning a barrier in said inactive region of said device wafer, said barrier being formed having a second height above said surface of said device wafer, said second height being greater than said first height of said multiple terminal elements, wherein said barrier does not contact said first and second sets of said bond pads;
coupling a cap wafer to said device wafer to form a wafer structure, said cap wafer covering each of said semiconductor dies; p 1 removing portions of said cap wafer to expose said multiple terminal elements, wherein said barrier substantially prevents said portions from contacting said multiple terminal elements when said portion of said cap wafer is removed; and
singulating said wafer structure to produce multiple semiconductor devices, each of said semiconductor devices including a portion of said device wafer having at least one of said semiconductor dies formed thereon and a section of said cap wafer covering part of said at least one semiconductor die with said terminal elements being exposed.
12. A method as claimed in claim 11 wherein said forming and said positioning operations comprise:
depositing a first structural layer on said device wafer;
forming said multiple terminal elements and a first layer of said barrier in said first structural layer, wherein said first height of said multiple terminal elements corresponds to a depth of said first structural layer;
depositing a second structural layer on said device wafer; and
forming a second layer of said barrier in said second structural layer, said second layer overlying said first layer to produce said second height of said barrier.
13. A method as claimed in claim 11 wherein:
said forming operation additionally forms said multiple terminal elements as multiple conductive lines electrically interconnecting said microelectronic device and said bond pads; and
said positioning operation positions another barrier in each of multiple inactive regions between pairs of said multiple conductive lines.