CMOS image sensor having double gate insulator therein
A method for manufacturing a CMOS image sensor includes: preparing a semiconductor substrate incorporating therein a p-type epitaxial layer by epitaxially growing up an upper portion of the semiconductor substrate; forming a pixel array in one predetermined location of the semiconductor substrate, the pixel array having a plurality of transistors and a photodiode therein, wherein each transistor employs a gate insulator with a thickness ranging from 40 Å to 90 Å; and forming a logic circuit in the other predetermined location of the semiconductor substrate, the logic circuit having at least one transistor, wherein the transistor employs a gate insulator with a thickness ranging from 5 Å to 40 Å.
1. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:
a semiconductor substrate having a pixel array area and a logic circuit area, wherein the pixel array area is bounded by the logic circuit area and is isolated from the logic circuit area by a field oxide region;
a pixel array formed in the pixel array area of the semiconductor substrate, wherein the pixel array includes a plurality of MOSFET transistors each having a gate with a gate insulating layer; and
a logic circuit formed in the logic circuit area of the semiconductor substrate, wherein the logic circuit is configured to process signals received from the pixel array, and wherein the logic circuit includes a plurality of MOSFET transistors each having a gate with a gate insulating layer;
wherein the gate insulating layers of all MOSFET transistors in the pixel array are thicker than the gate insulating layers of each MOSFET transistor in the logic circuit.
2. The CMOS image sensor of claim 1 , wherein each MOSFET transistor in the pixel array includes, as its gate insulating layer, a double layer of insulating material, and wherein each MOSFET transistor in the logic circuit includes, as its gate insulating layer, a single layer of insulating material.
3. The CMOS image sensor of claim 2 , wherein the single layer of insulating material has a thickness ranging from about 10 Å to about 40 Å, and wherein the double layer of insulating material has a thickness ranging from about 40 Å to about 90 Å.
4. The CMOS image sensor of claim 1 , wherein the semiconductor substrate includes a p-type epitaxial layer having doped regions configured to form the plurality of MOSFET transistors in the pixel array, and wherein the gate insulating layers of the plurality of MOSFET transistors in the pixel array include a layer of thermally-oxidized silicon oxide (SiO2) formed over the p-type epitaxial layer.
5. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:
a semiconductor substrate including a pixel array area and a logic circuit area located adjacent the pixel array area, wherein the pixel array area and logic circuit area are isolated from one another by an isolation region;
pixel sensors formed by MOSFET transistors in the pixel array area and arranged in a pixel array, wherein all of the MOSFET transistors in the pixel array area have a gate with a gate insulating layer of a first thickness; and
a logic circuit formed by MOSFET transistors in the logic circuit area, wherein the logic circuit is configured to process signals received from the pixel array, and wherein the MOSFET transistors in the logic circuit area have gates with gate insulating layers of a second thickness;
wherein the first thickness is greater than the second thickness.
6. The CMOS image sensor of claim 5 , wherein each MOSFET transistor forming the pixel sensors in the pixel array includes, as its gate insulating layer, a double layer of insulating material having the first thickness, and wherein some of the MOSFET transistors forming the logic circuit include, as their gate insulating layer, a single layer of insulating material having the second thickness.
7. The CMOS image sensor of claim 2 , wherein the single layer of insulating material has a thickness ranging from about 10 Å to about 40 Å, and wherein the double layer of insulating material has a thickness ranging from about 40 Å to about 90 Å.
8. The CMOS image sensor of claim 5 , wherein each MOSFET transistor in the pixel array includes, as its gate insulating layer, a double layer of insulating material, and wherein each MOSFET transistor in the logic circuit includes, as its gate insulating layer, a single layer of insulating material.
9. The CMOS image sensor of claim 5 , wherein the second thickness has a range from about 10 Å to about 40 Å, and wherein the first thickness has a range from about 40 Å to about 90 Å.
10. The CMOS image sensor of claim 5 , wherein the isolation region comprises a field oxide surrounding the pixel array area.
11. An image sensor, comprising:
a semiconductor substrate having a logic circuit region including a logic circuit and a pixel array region including a pixel array circuit, wherein the logic circuit region and pixel array region are immediately proximate one another and isolated by a field oxide region;
a plurality of MOSFET transistors configured to form the logic circuit in the logic circuit region; and
a plurality of MOSFET transistors configured to form the pixel array circuit in the pixel array region, wherein the plurality of MOSFET transistors of the logic circuit are electrically connected to the plurality of MOSFET transistors configured to form the pixel array circuit to thereby process signals received from the pixel array circuit;
wherein each of the plurality of MOSFET transistors configured to form the logic circuit includes a gate insulating layer having a first layer thickness, wherein all of the plurality of MOSFET transistors configured to form the pixel array circuit include a gate insulating layer having a second layer thickness, and wherein the first layer thickness is less than the second layer thickness.
12. The image sensor of claim 11 , wherein the second layer thickness is approximately twice the first layer thickness.
13. The image sensor of claim 11 , wherein the first layer thickness has a thickness ranging from about 10 Åto about 40 Å, and wherein the second layer thickness has a thickness ranging from about 40 Åto about 90 Å.